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DS1815-20+T&R PDF预览

DS1815-20+T&R

更新时间: 2024-11-14 14:41:51
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
5页 119K
描述
Power Supply Support Circuit, Fixed, 1 Channel, +2.55VV, CMOS, PBCY3, TO-92, ROHS COMPLIANT, 3 PIN

DS1815-20+T&R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TO-92
包装说明:TO-92, SIP3,.1,50针数:3
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
可调阈值:NO模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码:O-PBCY-T3JESD-609代码:e3
信道数量:1功能数量:1
端子数量:3最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TO-92封装等效代码:SIP3,.1,50
封装形状:ROUND封装形式:CYLINDRICAL
峰值回流温度(摄氏度):260电源:1.2/5.5 V
认证状态:Not Qualified子类别:Power Management Circuits
最大供电电流 (Isup):0.035 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:1.27 mm
端子位置:BOTTOM阈值电压标称:+2.55V
处于峰值回流温度下的最长时间:30Base Number Matches:1

DS1815-20+T&R 数据手册

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DS1815  
3.3V EconoReset with Push-Pull Output  
www.maxim-ic.com  
FEATURES  
PIN ASSIGNMENT  
C Automatically restarts a microprocessor after  
power failure  
3
DALLAS  
DS1815  
Econo  
C Maintains reset for 150ms after VCC returns to  
an in-tolerance condition  
Reset  
C Reduces need for discrete components  
C Precision temperature-compensated voltage  
reference and voltage sensor  
1
2
TOP VIEW  
SOT-23 PACKAGE  
See Mech.  
C Accurate 5%, 10% or 20% power monitoring  
C Low-cost TO-92 or space saving surface-  
mount SOT-23 packages available  
Drawings Section  
On Website  
1 2 3  
1 2 3  
C Push-pull output for low current operation  
C Operating temperature -40LC to +85LC  
BOTTOM VIEW  
TO-92 PACKAGE  
See Mech.  
Drawings Section  
On Website  
PIN DESCRIPTION  
TO-92  
1
2
3
RST  
VCC  
Active Low Reset Output  
Power Supply  
GND  
Ground  
SOT-23  
1
2
3
RST  
VCC  
Active Low Reset Output  
Power Supply  
GND  
Ground  
DESCRIPTION  
The DS1815 EconoReset uses a precision temperature reference and comparator circuit to monitor the  
status of the power supply (VCC). When an out-of-tolerance condition is detected, an internal power-fail  
signal is generated which forces reset to the active state. When VCC returns to an in-tolerance condition,  
the reset signal is kept in the active state for approximately 150ms to allow the power supply and  
processor to stabilize.  
1 of 5  
041002  

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