DS17285-5+

更新时间： 2024-02-18 08:02:45

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
31页	324K
描述
Real-Time Clocks

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DS17285-5+ 数据手册

Real-Time Clocks

Pin Description (continued)

NAME

FUNCTION

Active-Low Chip-Select Input. This pin must be asserted low during a bus cycle for the

device to be accessed. CS must be kept in the active state during RD and WR. Bus cycles

that take place without asserting CS latch addresses, but no access occurs.

Address Latch Enable Input, Active High. This input pin is used to demultiplex the

address/data bus. The falling edge of ALE causes the address to be latched within the

device.

ALE

Active-Low Write Input. This pin defines the period during which data is written to the

addressed register.

Active-Low Read Input. This pin identifies the period when the device drives the bus with

read data. It is an enable signal for the output buffers of the device.

Active-Low Kickstart Input. When V is removed from the device, the system can be

powered on in response to an active-low transition on the KS pin, as might be generated

from a key closure. V

set to 1 if the kickstart function is used, and the KS pin must be pulled up to the V

must be present and auxiliary-battery-enable bit (ABE) must be

BAUX

supply. While V is applied, the KS pin can be used as an interrupt input. If not used, KS

must be grounded and ABE set to 0.

Active-Low Interrupt Request. This pin is an active-low output that can be used as an

interrupt input to a processor. The IRQ output remains low as long as the status bit causing

the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ

pin, the application software must clear all enabled flag bits contributing to the pin’s active

state. When no interrupt conditions are present, the IRQ level is in the high-impedance

state. Multiple interrupting devices can be connected to an IRQ bus, provided that they are

IRQ

all open drain. The IRQ pin requires an external pullup resistor to V

Connection for Primary Battery. This supply input is used to power the normal clock

functions when V is absent. Diodes placed in series between V and the battery can

BAT

prevent proper operation. If V

is not required, the pin must be grounded. UL recognized

BAT

to ensure against reverse charging current when used with a lithium battery (www.maxim-

ic.com/qa/info/ul). This pin is missing (N.C.) on the EDIP package.

245/DS187

_____________________________________________________________________

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DS17285-5+ 替代型号

型号	品牌	替代类型	描述	数据表
DS17285SN-5+	MAXIM	类似代替	Real-Time Clocks
DS17285S-5	MAXIM	类似代替	Real-Time Clocks
DS17285-5	MAXIM	类似代替	Real-Time Clocks

与DS17285-5+相关器件

型号	品牌	获取价格	描述	数据表
DS17285-DS17287	DALLAS	获取价格	3V/5V Real-Time Clock
DS17285E3	MAXIM	获取价格	Real-Time Clocks
DS17285E-3	MAXIM	获取价格	Real-Time Clocks
DS17285E-3	DALLAS	获取价格	3V/5V Real-Time Clock
DS17285E-3+	MAXIM	获取价格	Real-Time Clocks
DS17285E5	MAXIM	获取价格	Real-Time Clocks
DS17285E-5	MAXIM	获取价格	Real-Time Clocks
DS17285E-5	DALLAS	获取价格	3V/5V Real-Time Clock
DS17285E-5+	MAXIM	获取价格	Real-Time Clocks
DS17285EN-	MAXIM	获取价格	Real-Time Clocks

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