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DS1721S/T&R PDF预览

DS1721S/T&R

更新时间: 2024-01-27 05:10:16
品牌 Logo 应用领域
美信 - MAXIM 传感器换能器输出元件监控
页数 文件大小 规格书
17页 269K
描述
Serial Switch/Digital Sensor, 12 Bit(s), 1Cel, Rectangular, 8 Pin, Surface Mount, 0.150 INCH, SOIC-8

DS1721S/T&R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSSOP8,.19
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.36最大精度(摄氏度):1 Cel
主体宽度:3 mm主体高度:1.1 mm
主体长度或直径:3 mm外壳:PLASTIC
JESD-609代码:e3安装特点:SURFACE MOUNT
位数:12端子数量:8
最大工作电流:1.25 mA最高工作温度:125 °C
最低工作温度:-55 °C输出接口类型:2-WIRE INTERFACE
封装主体材料:PLASTIC/EPOXY封装等效代码:TSSOP8,.19
封装形状/形式:SQUARE电源:3/5 V
传感器/换能器类型:TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL子类别:Other Sensors
最大供电电压:5.5 V最小供电电压:2.7 V
表面贴装:YES端子面层:Matte Tin (Sn)
端接类型:SOLDERBase Number Matches:1

DS1721S/T&R 数据手册

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DS1721  
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 5  
Figure 6 details how data transfer is accomplished on the two-wire bus. Depending upon the state of the  
R/ W bit, two types of data transfer are possible:  
Data transfer from a master transmitter to a slave receiver. The 1st byte transmitted by the master is  
the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each  
received byte.  
Data transfer from a slave transmitter to a master receiver. The 1st byte (the slave address) is  
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data  
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received  
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.  
The master device generates all of the serial clock pulses and the START and STOP conditions. A  
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START  
condition is also the beginning of the next serial transfer, the bus will not be released.  
The DS1721 may operate in the following two modes:  
Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is  
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the  
beginning and end of a serial transfer. Address recognition is performed by hardware after reception of  
the slave address and direction bit.  
Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However,  
in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted  
on SDA by the DS1721 while the serial clock is input on SCL. START and STOP conditions are  
recognized as the beginning and end of a serial transfer.  
8 of 17  

DS1721S/T&R 替代型号

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