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DS1721S/T&R PDF预览

DS1721S/T&R

更新时间: 2024-01-17 06:22:00
品牌 Logo 应用领域
美信 - MAXIM 传感器换能器输出元件监控
页数 文件大小 规格书
17页 269K
描述
Serial Switch/Digital Sensor, 12 Bit(s), 1Cel, Rectangular, 8 Pin, Surface Mount, 0.150 INCH, SOIC-8

DS1721S/T&R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSSOP8,.19
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.36最大精度(摄氏度):1 Cel
主体宽度:3 mm主体高度:1.1 mm
主体长度或直径:3 mm外壳:PLASTIC
JESD-609代码:e3安装特点:SURFACE MOUNT
位数:12端子数量:8
最大工作电流:1.25 mA最高工作温度:125 °C
最低工作温度:-55 °C输出接口类型:2-WIRE INTERFACE
封装主体材料:PLASTIC/EPOXY封装等效代码:TSSOP8,.19
封装形状/形式:SQUARE电源:3/5 V
传感器/换能器类型:TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL子类别:Other Sensors
最大供电电压:5.5 V最小供电电压:2.7 V
表面贴装:YES端子面层:Matte Tin (Sn)
端接类型:SOLDERBase Number Matches:1

DS1721S/T&R 数据手册

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DS1721  
If the user does not wish to take advantage of the thermostat capabilities of the DS1721, the 24 bits can be  
used for general storage of system data that need not be maintained following a power loss. However, the  
TOUT pin should be left floating if general data is stored in TH/TL.  
2-WIRE SERIAL DATA BUS  
The DS1721 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data  
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls  
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must  
be controlled by a master device which generates the serial clock (SCL), controls the bus access, and  
generates the START and STOP conditions. The DS1721 operates as a slave on the 2-wire bus.  
Connections to the bus are made via the open-drain I/O lines SDA and SCL.  
The following bus protocol has been defined (See Figure 5):  
Sꢀ Data transfer may be initiated only when the bus is not busy.  
Sꢀ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in  
the data line while the clock line is high will be interpreted as control signals.  
Accordingly, the following bus conditions have been defined:  
Bus not busy: Both data and clock lines remain HIGH.  
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,  
defines a START condition.  
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is  
HIGH, defines the STOP condition.  
Data valid: The state of the data line represents valid data when, after a START condition, the data line  
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed  
during the LOW period of the clock signal. There is one clock pulse per bit of data.  
Each data transfer is initiated with a START condition and terminated with a STOP condition. The  
number of data bytes transferred between START and STOP conditions is not limited, and is determined  
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th  
bit.  
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)  
are defined. The DS1721 works in both modes.  
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the  
reception of each byte. The master device must generate an extra clock pulse which is associated with this  
acknowledge bit.  
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a  
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of  
course, setup and hold times must be taken into account. A master must signal an end of data to the slave  
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,  
the slave must leave the data line HIGH to enable the master to generate the STOP condition.  
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