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DS1624S+T&R PDF预览

DS1624S+T&R

更新时间: 2024-01-18 06:24:20
品牌 Logo 应用领域
美信 - MAXIM 存储
页数 文件大小 规格书
20页 667K
描述
Digital Thermometer and Memory

DS1624S+T&R 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active包装说明:SOP8,.3
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.37Is Samacsys:N
其他特性:COMPLIANCE TO MIL-208主体宽度:5.285 mm
主体高度:1.98 mm主体长度或直径:5.31 mm
外壳:PLASTICJESD-609代码:e3
安装特点:SURFACE MOUNT位数:13
端子数量:8最大工作电流:1 mA
最高工作温度:125 °C最低工作温度:-55 °C
输出接口类型:2-WIRE INTERFACE封装主体材料:PLASTIC/EPOXY
封装等效代码:SOP8,.3封装形状/形式:RECTANGULAR
电源:3/5 V传感器/换能器类型:TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL
子类别:Other Sensors/Transducers最大供电电压:5.5 V
最小供电电压:2.7 V表面贴装:YES
端子面层:Matte Tin (Sn)端接类型:SOLDER
Base Number Matches:1

DS1624S+T&R 数据手册

 浏览型号DS1624S+T&R的Datasheet PDF文件第1页浏览型号DS1624S+T&R的Datasheet PDF文件第2页浏览型号DS1624S+T&R的Datasheet PDF文件第4页浏览型号DS1624S+T&R的Datasheet PDF文件第5页浏览型号DS1624S+T&R的Datasheet PDF文件第6页浏览型号DS1624S+T&R的Datasheet PDF文件第7页 
DS1624  
DS1624 FUNCTIONAL BLOCK DIAGRAM Figure 1  
STATUS REGISTER &  
VDD  
CONTROL LOGIC  
SCL  
SDA  
TEMPERATURE SENSOR  
ADDRESS  
AND  
I/O CONTROL  
EEPROM MEMORY (256 BYTES)  
A0  
A1  
A2  
GND  
2-WIRE SERIAL DATA BUS  
The DS1624 supports a bi–directional two–wire bus and data transmission protocol. A device that sends  
data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that  
controls the message is called a “master”. The devices that are controlled by the master are “slaves”. The  
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,  
and generates the START and STOP conditions. The DS1624 operates as a slave on the two–wire bus.  
Connections to the bus are made via the open–drain I/O lines SDA and SCL. The following bus protocol  
has been defined (See Figure 2):  
Data transfer may be initiated only when the bus is not busy.  
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in  
the data line while the clock line is high will be interpreted as control signals.  
Accordingly, the following bus conditions have been defined:  
Bus not busy: Both data and clock lines remain HIGH.  
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,  
defines a START condition.  
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is  
HIGH, defines the STOP condition.  
3 of 20  

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