Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS15BR400TSQ

DS15BR400TSQ

更新时间： 2024-02-19 03:20:02

品牌	Logo	应用领域
美国国家半导体 - NSC		线路驱动器或接收器驱动程序和接口接口集成电路中继器
页数	文件大小	规格书
11页	645K
描述
4-Channel LVDS Buffer/Repeater with Pre-Emphasis

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中文翻译

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技术参数
数据手册

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DS15BR400TSQ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	TFQFP, TQFP48,.35SQ
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.1
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	1.25	Samacsys Description：	LVDS Interface IC 4ch LVDS Buffer/Repeater
差分输出：	YES	驱动器位数：	4
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	4
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	最小输出摆幅：	2 V
输出特性：	DIFFERENTIAL	最大输出低电流：	0.00001 A
输出极性：	COMPLEMENTARY	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP48,.35SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	最大接收延迟：	2 ns
接收器位数：	4	座面最大高度：	1.2 mm
子类别：	Line Driver or Receivers	最大压摆率：	215 mA
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	电源电压1-最大：	3.6 V
电源电压1-分钟：	3 V	电源电压1-Nom：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	最大传输延迟：	2 ns
宽度：	7 mm

DS15BR400TSQ 数据手册

INPUT FAILSAFE BIASING

Application Information

External pull up and pull down resistors may be used to

provide enough of an offset to enable an input failsafe under

open-circuit conditions. This configuration ties the positive

LVDS input pin to V_DDthru a pull up resistor and the negative

LVDS input pin is tied to GND by a pull down resistor. The

pull up and pull down resistors should be in the 5kΩ to 15kΩ

range to minimize loading and waveform distortion to the

driver. The common-mode bias point ideally should be set to

approximately 1.2V. Please refer to application note AN-

1194 “Failsafe Biasing of LVDS Interfaces” for more informa-

tion.

INTERNAL TERMINATIONS

The DS15BR400 has integrated termination resistors on

both the input and outputs. The inputs have a 100Ω resistor

across the differential pair, placing the receiver termination

as close as possible to the input stage of the device. The

LVDS outputs also contain an integrated 100Ω ohm termi-

nation resistor, this resistor is used to minimize the output

return loss and does not take the place of the 100 ohm

termination at the inputs to the receiving device. The inte-

grated terminations improve signal integrity and decrease

the external component count resulting in space savings.

The DS15BR401 has 100Ω output terminations only.

DECOUPLING

Each power or ground lead of the DS15BR400 should be

connected to the PCB through a low inductance path. For

best results, one or more vias are used to connect a power

or ground pin to the nearby plane. Ideally, via placement is

immediately adjacent to the pin to avoid adding trace induc-

tance. Placing power plane closer to the top of the board

reduces effective via length and its associated inductance.

OUTPUT CHARACTERISTICS

The output characteristics of the DS15BRB400/DS15BR401

have been optimized for point-to-point backplane and cable

applications, and are not intended for multipoint or multidrop

signaling.

Bypass capacitors should be placed close to VDD pins.

Small physical size capacitors, such as 0402, X7R, surface

mount capacitors should be used to minimize body induc-

tance of capacitors. Each bypass capacitor is connected to

the power and ground plane through vias tangent to the pads

of the capacitor. An X7R surface mount capacitor of size

0402 has about 0.5 nH of body inductance. At frequencies

above 30 MHz or so, X7R capacitors behave as low imped-

ance inductors. To extend the operating frequency range to a

few hundred MHz, an array of different capacitor values like

100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in

parallel. The most effective bypass capacitor can be built

using sandwiched layers of power and ground at a separa-

tion of 2–3 mils. With a 2 mil FR4 dielectric, there is approxi-

mately 500 pF per square inch of PCB.

POWERDOWN MODE

The PWDN input activates a hardware powerdown mode.

When the powerdown mode is active (PWDN=L), all input

and output buffers and internal bias circuitry are powered off.

When exiting powerdown mode, there is a delay associated

with turning on bandgap references and input/output buffer

circuits as indicated in the LVDS Output Switching Charac-

teristics

PRE-EMPHASIS

Pre-emphasis dramatically reduces ISI jitter from long or

lossy transmission media. One pin is used to select the

pre-emphasis level for all outputs, off or on. The pre-

emphasis boost is approximately 6 dB at 750 MHz.

The center dap of the LLP package housing the DS15BR400

should be connected to a ground plane through an array of

vias. The via array reduces the effective inductance to

ground and enhances the thermal performance of the LLP

package.

Pre-emphasis Control Selection Table

PEM

Pre-Emphasis

Off

www.national.com

1...5 6 789 10 11

中文翻译

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与DS15BR400TSQ相关器件

型号	品牌	描述	获取价格	数据表
DS15BR400TSQ/NOPB	NSC	IC LINE TRANSCEIVER, QCC32, LLP-32, Line Driver or Receiver	获取价格
DS15BR400TSQ/NOPB	TI	具有预加重功能的 4 通道 LVDS 缓冲器/中继器 \| RTV \| 32 \| -40 t	获取价格
DS15BR400TSQX	NSC	4-Channel LVDS Buffer/Repeater with Pre-Emphasis	获取价格
DS15BR400TVS	TI	具有预加重功能的 4 通道 LVDS 缓冲器/中继器 \| PFB \| 48 \| -40 t	获取价格
DS15BR400TVS	NSC	4-Channel LVDS Buffer/Repeater with Pre-Emphasis	获取价格
DS15BR400TVS/NOPB	TI	具有预加重功能的 4 通道 LVDS 缓冲器/中继器 \| PFB \| 48 \| -40 t	获取价格

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