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DS15BR400 PDF预览

DS15BR400

更新时间: 2024-01-17 05:03:53
品牌 Logo 应用领域
德州仪器 - TI 中继器
页数 文件大小 规格书
23页 624K
描述
具有预加重功能的 4 通道 LVDS 缓冲器/中继器

DS15BR400 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TFQFP, TQFP48,.35SQ
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.25Samacsys Description:LVDS Interface IC 4ch LVDS Buffer/Repeater
差分输出:YES驱动器位数:4
输入特性:DIFFERENTIAL接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
湿度敏感等级:3功能数量:4
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:2 V
输出特性:DIFFERENTIAL最大输出低电流:0.00001 A
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP48,.35SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:2 ns
接收器位数:4座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大压摆率:215 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V电源电压1-最大:3.6 V
电源电压1-分钟:3 V电源电压1-Nom:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:2 ns
宽度:7 mm

DS15BR400 数据手册

 浏览型号DS15BR400的Datasheet PDF文件第5页浏览型号DS15BR400的Datasheet PDF文件第6页浏览型号DS15BR400的Datasheet PDF文件第7页浏览型号DS15BR400的Datasheet PDF文件第9页浏览型号DS15BR400的Datasheet PDF文件第10页浏览型号DS15BR400的Datasheet PDF文件第11页 
DS15BR400, DS15BR401  
SNLS224G AUGUST 2006REVISED APRIL 2013  
www.ti.com  
APPLICATION INFORMATION  
INTERNAL TERMINATIONS  
The DS15BR400 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω  
resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the  
device. The LVDS outputs also contain an integrated 100ohm termination resistor, this resistor is used to  
minimize the output return loss and does not take the place of the 100 ohm termination at the inputs to the  
receiving device. The integrated terminations improve signal integrity and decrease the external component  
count resulting in space savings. The DS15BR401 has 100output terminations only.  
OUTPUT CHARACTERISTICS  
The output characteristics of the DS15BRB400/DS15BR401 have been optimized for point-to-point backplane  
and cable applications, and are not intended for multipoint or multidrop signaling.  
POWERDOWN MODE  
The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all  
input and output buffers and internal bias circuitry are powered off. When exiting powerdown mode, there is a  
delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS  
Output Switching Characteristics.  
Upon asserting the power down function (PWDN = Low), and if the Pre-emphasis feature is enable, it is possible  
for the driver output to source current for a short amount of time lifting the output common mode to VDD. To  
prevent this occurrence, a load discharge pull down path can be used on either output (1 kto ground  
recommended). Alternately, a commonly deployed external failsafe network will also provide this path (see  
INPUT FAILSAFE BIASING). The occurrence of this is application dependant, and parameters that will effect if  
this is of concern include: AC coupling, use of the powerdown feature, presence of the discharge path, presence  
of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream LVDS  
Receiver.  
PRE-EMPHASIS  
Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. One pin is used to select the  
pre-emphasis level for all outputs, off or on. The pre-emphasis boost is approximately 6 dB at 750 MHz.  
Table 1. Pre-emphasis Control Selection Table  
PEM  
Pre-Emphasis  
0
1
Off  
On  
INPUT FAILSAFE BIASING  
Failsafe biasing of the LVDS link should be considered if the downstream Receiver is ON and enabled when the  
source is in TRI-STATE, powered off, or removed. This will set a valid known input state to the active receiver.  
This is accomplished by using a pull up resistor to VDD on the ‘plus’ line, and a pull down resistor to GND on the  
‘minus’ line. Resistor values are in the 750 Ohm to several krange. The exact value depends upon the desired  
common mode bias point, termination resistor(s) and desired input differential voltage setting. Please refer to  
application note AN-1194 “Failsafe Biasing of LVDS interfaces” (SNLA051) for more information and a general  
discussion.  
DECOUPLING  
Each power or ground lead of the DS15BR400 should be connected to the PCB through a low inductance path.  
For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via  
placement is immediately adjacent to the pin to avoid adding trace inductance. Placing power plane closer to the  
top of the board reduces effective via length and its associated inductance.  
8
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Copyright © 2006–2013, Texas Instruments Incorporated  
Product Folder Links: DS15BR400 DS15BR401  

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