Datasheet > DS1267E-050/TR

DS1267E-050/TR

更新时间： 2024-02-12 13:43:17

品牌	Logo	应用领域
达拉斯 - DALLAS		电位器
页数	文件大小	规格书
12页	314K
描述
Dual Digital Potentiometer Chip

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技术参数
数据手册

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DS1267E-050/TR 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	TSSOP,	针数：	20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.77
控制接口：	3-WIRE SERIAL	转换器类型：	DIGITAL POTENTIOMETER
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
长度：	6.5 mm	湿度敏感等级：	1
功能数量：	2	位置数：	256
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	电阻定律：	LINEAR
座面最大高度：	1.1 mm	标称供电电压：	5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	标称总电阻：	50000 Ω
宽度：	4.4 mm	Base Number Matches：	1

DS1267E-050/TR 数据手册

DS1267

The C_OUToutput of the DS1267 can be used to drive the DQ input of another DS1267. When connecting

multiple devices, the total number of bits transmitted is always 17 times the number of DS1267s in the

daisy chain.

An optional feedback resistor can be placed between the C_OUTterminal of the last device and the first

DS1267 DQ input, thus allowing the controlling processor to read as well as write data or circularly clock

data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1

to 10 kohms.

When reading data via the C_OUTpin and isolation resistor, the DQ line is left floating by the reading

device. When RST is driven high, bit 17 is present on the C_OUTpin, which is fed back to the input DQ

pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the

first position of the I/O shift register and bit 16 becomes present on C_OUTand DQ of the next device. After

17 bits (or 17 times the number of DS1267s in the daisy chain), the data has shifted completely around

and back to its original position. When RST transitions to the low state to end data transfer, the value (the

same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.

ABSOLUTE AND RELATIVE LINEARITY

Absolute linearity is defined as the difference between the actual measured output voltage and the

expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute

linearity is given in terms of a minimum increment or expected output when the wiper is moved one

position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 10/512 volts.

The equation for absolute linearity is given as follows:

(1)

ABSOLUTE LINEARITY

AL={V_O(actual) - V_O(expected)}/MI

Relative Linearity is a measure of error between two adjacent wiper position points and is given in terms

of MI by equation (2).

(2)

RELATIVE LINEARITY

RL={V_O(n+1) - V_O(n)}/MI

Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267 at 25°C.

The specification for absolute linearity of the DS1267 is ±0.75 MI typical. The specification for relative

linearity of the DS1267 is ±0.3 MI typical.

5 of 12

102199

1 2 3 456 7 8...12

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与DS1267E-050/TR相关器件

型号	品牌	描述	获取价格	数据表
DS1267E-10	MAXIM	Digital Potentiometer, 2 Func, 10000ohm, 3-wire Serial Control Interface, 256 Positions, C	获取价格
DS1267E-10+T&R	MAXIM	Digital Potentiometer, 2 Func, 10000ohm, 3-wire Serial Control Interface, 256 Positions, P	获取价格
DS1267E-100	DALLAS	Dual Digital Potentiometer Chip	获取价格
DS1267E-100/T&R	MAXIM	Digital Potentiometer, 2 Func, 100000ohm, 3-wire Serial Control Interface, 256 Positions,	获取价格
DS1267E-100/TR	DALLAS	Dual Digital Potentiometer Chip	获取价格
DS1267E-100+	MAXIM	Digital Potentiometer, 2 Func, 100000ohm, 3-wire Serial Control Interface, 256 Positions,	获取价格

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