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DS1232LP PDF预览

DS1232LP

更新时间: 2024-11-30 14:57:27
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
7页 99K
描述
低功耗、MicroMonitor芯片

DS1232LP 数据手册

 浏览型号DS1232LP的Datasheet PDF文件第2页浏览型号DS1232LP的Datasheet PDF文件第3页浏览型号DS1232LP的Datasheet PDF文件第4页浏览型号DS1232LP的Datasheet PDF文件第5页浏览型号DS1232LP的Datasheet PDF文件第6页浏览型号DS1232LP的Datasheet PDF文件第7页 
DS1232LP/LPS  
Low Power MicroMonitor Chip  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
Super-low power version of DS1232  
50 µA quiescent current  
VCC  
PBRST  
1
2
3
4
8
NC  
PBRST  
NC  
1
2
3
4
5
16  
15  
14  
13  
12  
NC  
VCC  
NC  
ST  
TD  
ST  
7
6
5
Halts and restarts an out-of-control  
microprocessor  
Automatically restarts microprocessor after  
power failure  
Monitors pushbutton for external override  
Accurate 5% or 10% microprocessor power  
supply monitoring  
RST  
RST  
TOL  
TD  
NC  
NC  
GND  
TOL  
NC  
6
7
8
11  
10  
9
RST  
NC  
DS1232LP 8-Pin DIP (300-mil)  
See Mech. Drawings Section  
GND  
RST  
DS1232LPS 16-Pin SOIC (300-mil)  
See Mech. Drawings Section  
8-pin DIP, 8-pin SOIC or space saving µ-SOP  
package available  
Optional 16-pin SOIC package available  
Industrial temperature -40°C to +85°C  
available, designated N  
VCC  
ST  
PBRST  
TD  
1
2
3
4
8
7
6
5
8
1
2
3
4
PBRST  
TD  
VCC  
ST  
7
6
5
RST  
RST  
TOL  
TOL  
RST  
RST  
GND  
GND  
DS1232LPµ (118-mil µ-SOP)  
See Mech. Drawings Section  
DS1232LPS-2 8-Pin SOIC (150-mil)  
See Mech. Drawings Section  
PIN DESCRIPTION  
PBRST  
TD  
- Pushbutton Reset Input  
- Time Delay Set  
TOL  
GND  
RST  
- Selects 5% or 10% VCC Detect  
- Ground  
- Reset Output (Active High)  
RST  
- Reset Output (Active Low, open  
drain)  
ST  
- Strobe Input  
VCC  
- +5 Volt Power  
DESCRIPTION  
The DS1232LP/LPS Low Power MicroMonitor Chip monitors three vital conditions for a  
microprocessor: power supply, software execution, and external over-ride. First, a precision temperature-  
compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance  
condition occurs, an internal power-fail signal is generated which forces reset to the active state. When  
VCC returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of  
250 ms to allow the power supply and processor to stabilize.  
1 of 7  
111899  

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