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DS1231-50+ PDF预览

DS1231-50+

更新时间: 2024-11-29 12:58:19
品牌 Logo 应用领域
美信 - MAXIM 电源电路电源管理电路光电二极管监控
页数 文件大小 规格书
9页 70K
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DS1231-50+ 数据手册

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DS1231/S  
DS1231/S  
Power Monitor Chip  
FEATURES  
PIN ASSIGNMENT  
Warns processor of an impending power failure  
1
2
3
4
8
7
VCC  
NMI  
IN  
MODE  
TOL  
Provides time for an orderly shutdown  
Prevents processor from destroying nonvolatile  
memory during power transients  
RST  
RST  
6
5
GND  
Automatically restarts processor after power is  
restored  
DS1231 8–Pin DIP  
(300 MIL)  
See Mech. Drawings  
Section  
Suitable for linear or switching power supplies  
Adjusts to hold time of the power supply  
NC  
16  
15  
NC  
IN  
1
2
3
VCC  
NC  
Supplies necessary signals for processor interface  
NC  
14  
13  
MODE  
NMI  
NC  
4
5
Accurate 5% or 10% V monitoring  
CC  
NC  
12  
6
7
TOL  
Replaces power-up reset circuitry  
No external capacitors required  
11  
10  
RST  
NC  
NC  
9
GND  
8
RST  
Optional 16-pin SOIC surface mount package  
DS1231S 16–Pin SOIC  
(300 MIL)  
See Mech. Drawings  
Section  
PIN DESCRIPTION  
IN  
Input  
MODE  
TOL  
GND  
RST  
RST  
NMI  
Selects input pin characteristics  
Selects 5% or 10% V detect  
Ground  
Reset (Active High)  
Reset (Active Low, open drain)  
Non–Maskable Interrupt  
+5V Supply  
CC  
V
CC  
NC  
No Connections  
DESCRIPTION  
The DS1231 Power Monitor Chip uses a precise tem-  
perature-compensatedreference circuit whichprovides  
an orderly shutdown and an automatic restart of a pro-  
cessor-basedsystem. Asignalwarningofanimpending  
power failure is generated well before regulated DC  
voltages go out of specification by monitoring high volt-  
age inputs to the power supply regulators. If line isola-  
tion is required a UL-approved opto-isolator can be di-  
rectly interfaced to the DS1231. The time for processor  
shutdown is directly proportional to the available  
hold-up time of the power supply. Just before the  
hold-up time is exhausted, the Power Monitor uncondi-  
tionally halts the processor to prevent spurious cycles  
by enabling Reset as V falls below a selectable 5 or  
CC  
10 percent threshold. When power returns, the proces-  
sor is held inactive until well after power conditions have  
stabilized, safeguarding any nonvolatile memory in the  
system from inadvertent data changes.  
022698 1/9  

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