Datasheet > DS1100LM-75

DS1100LM-75

更新时间： 2022-12-01 20:46:20

品牌	Logo	应用领域
达拉斯 - DALLAS		光电二极管
页数	文件大小	规格书
6页	57K
描述
Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8

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DS1100LM-75 数据手册

DS1100L

TERMINOLOGY

Period: The time elapsed between the leading edge of the first pulse and the leading edge of the

following pulse.

t_WI(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the

1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading

edge.

t_RISE(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the

input pulse.

t_FALL(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the

input pulse.

t_PLH(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input

pulse and the 1.5V point on the leading edge of any tap output pulse.

t_PHL(Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input

pulse and the 1.5V point on the trailing edge of any tap output pulse.

TEST SETUP DESCRIPTION

Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the

DS1100L. The input waveform is produced by a precision pulse generator under software control. Time

delays are measured by a time interval counter (20 ps resolution) connected between the input and each

tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements

are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.

TEST CONDITIONS INPUT:

Ambient Temperature: 25°C ± 3°C

Supply Voltage (V_CC): 53.3V ± 0.1V

Input Pulse:

High = 3.0V ± 0.1V

Low = 0.0V ± 0.1V

Source Impedance:

Rise and Fall Time:

Pulse Width:

50 Ohm Max.

3.0 ns Max. (measured between 10% and 90%)

500 ns

1 µs

Period:

OUTPUT:

Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on

the rising and falling edge.

NOTE:

Above conditions are for test only and do not restrict the operation of the device under other data sheet

conditions.

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