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DS1100LU-100 PDF预览

DS1100LU-100

更新时间: 2024-01-05 15:25:22
品牌 Logo 应用领域
达拉斯 - DALLAS 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
6页 158K
描述
3.3V 5-Tap Economy Timing Element Delay Line

DS1100LU-100 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:5 weeks
风险等级:5.05Is Samacsys:N
系列:1100JESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:SILICON DELAY LINE湿度敏感等级:1
功能数量:1抽头/阶步数:5
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出阻抗标称值(Z0):50 Ω
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
可编程延迟线:NOProp。Delay @ Nom-Sup:100 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Delay Lines最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
总延迟标称(td):100 ns宽度:3 mm
Base Number Matches:1

DS1100LU-100 数据手册

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PRELIMINARY  
DS1100L  
3.3V 5-Tap Economy Timing  
Element (Delay Line)  
www.maxim-ic.com  
PIN ASSIGNMENT  
FEATURES  
C All-Silicon Timing Circuit  
C Five Taps Equally Spaced  
C Delays are Stable and Precise  
C Both Leading- and Trailing-Edge Accuracy  
C 3.3V Version of the DS1100  
C Low-Power CMOS  
IN  
TAP 2  
TAP 4  
GND  
1
2
3
4
8
7
6
5
VCC  
TAP 1  
TAP 3  
TAP 5  
C TTL-/CMOS-compatible  
C Vapor-Phase and IR Solderable  
C Custom Delays Available  
C Fast-Turn Prototypes  
DS1100LZ SO (150mil)  
DS1100LU µSOP  
C Delays Specified Over Both Commercial and  
Industrial Temperature Ranges  
PIN DESCRIPTION  
TAP 1 to TAP 5  
- TAP Output Number  
- +3.3V  
VCC  
GND  
IN  
- Ground  
- Input  
DESCRIPTION  
The DS1100L is a 3.3V version of the DS1100. It is characterized for operation over the range 3.0V to  
3.6V. The DS1100L series delay lines have five equally spaced taps providing delays from 4ns to 500ns.  
These devices are offered in surface-mount packages to save PC board area. Low cost and superior  
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and  
industry-standard µSOP and SO packaging. The DS1100L 5-tap silicon delay line reproduces the input-  
logic state at the output after a fixed delay as specified by the extension of the part number after the dash.  
The DS1100L is designed to reproduce both leading and trailing edges with equal precision. Each tap is  
capable of driving up to ten 74LS loads.  
Dallas Semiconductor can customize standard products to meet special needs.  
1 of 6  
091201  

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