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DS1100-40 PDF预览

DS1100-40

更新时间: 2024-01-28 00:29:17
品牌 Logo 应用领域
达拉斯 - DALLAS 延迟线
页数 文件大小 规格书
6页 156K
描述
5-Tap Economy Timing Element Delay Line

DS1100-40 数据手册

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DS1100  
5-Tap Economy Timing  
Element (Delay Line)  
www.maxim-ic.com  
PIN ASSIGNMENT  
FEATURES  
C All-Silicon Timing Circuit  
C Five Taps Equally Spaced  
C 5V Operation  
IN  
TAP 2  
TAP 4  
GND  
1
2
3
4
8
7
6
5
VCC  
TAP 1  
TAP 3  
TAP 5  
C Delays are Stable and Precise  
C Both Leading- and Trailing-Edge Accuracy  
C Improved Replacement for DS1000  
C Low-Power CMOS  
C TTL/CMOS-Compatible  
DS1100M DIP (300mil)  
DS1100Z SO (150mil)  
DS1100U µSOP  
C Vapor-Phase, IR, and Wave Solderable  
C Custom Delays Available  
C Fast-Turn Prototypes  
C Delays Specified Over Both Commercial and  
Industrial Temperature Ranges  
PIN DESCRIPTION  
TAP 1 to TAP 5  
- TAP Output Number  
- +5V  
VCC  
GND  
IN  
- Ground  
- Input  
DESCRIPTION  
The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These  
devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and  
superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line  
and industry-standard DIP and SO packaging. The DS1100 5-tap silicon delay line reproduces the input-  
logic state at the output after a fixed delay as specified by the extension of the part number after the dash.  
The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap is  
capable of driving up to ten 74LS loads.  
Dallas Semiconductor can customize standard products to meet special needs.  
1 of 6  
091202  

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