DS1086LU+

更新时间： 2024-02-04 08:24:10

品牌	Logo	应用领域
美信 - MAXIM		模拟IC 信号电路光电二极管
页数	文件大小	规格书
17页	233K
描述
3.3V Spread-Spectrum EconOscillator

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技术参数
数据手册

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DS1086LU+ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	5.27	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.88 mm	湿度敏感等级：	1
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	133 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9116 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

DS1086LU+ 数据手册

3.3V Spread-Spectrum EconOscillator

DS1086L

ditions is not limited, and is determined by the master

device. The information is transferred byte-wise and

each receiver acknowledges with a ninth bit.

beginning of the next serial transfer, the bus is not

released.

The DS1086L can operate in the following two modes:

Within the bus specifications a standard mode (100kHz

clock rate) and a fast mode (400kHz clock rate) are

defined. The DS1086L works in both modes.

Slave receiver mode: Serial data and clock are

received through SDA and SCL. After each byte is

received, an acknowledge bit is transmitted. START

and STOP conditions are recognized as the beginning

and end of a serial transfer. Address recognition is per-

formed by hardware after reception of the slave

address and direction bit.

Acknowledge: Each receiving device, when

addressed, is obliged to generate an acknowledge

after the byte has been received. The master device

must generate an extra clock pulse that is associated

with this acknowledge bit.

Slave transmitter mode: The first byte is received and

handled as in the slave receiver mode. However, in this

mode, the direction bit indicates that the transfer direc-

tion is reversed. Serial data is transmitted on SDA by

the DS1086L while the serial clock is input on SCL.

START and STOP conditions are recognized as the

beginning and end of a serial transfer.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable LOW during the HIGH period

of the acknowledge-related clock pulse. Of course,

setup and hold times must be taken into account.

When the DS1086L EEPROM is being written to, it is

not able to perform additional responses. In this case,

the slave DS1086L sends a not acknowledge to any

data transfer request made by the master. It resumes

normal operation when the EEPROM operation is com-

plete.

Slave Address

Figure 5 shows the first byte sent to the device. It

includes the device identifier, device address, and the

R/W bit. The device address is determined by the

ADDR register.

A master must signal an end of data to the slave by not

generating an acknowledge bit on the last byte that has

been clocked out of the slave. In this case, the slave

must leave the data line HIGH to enable the master to

generate the STOP condition.

Registers/Commands

See Table 1 for the complete list of registers/com-

mands and Figure 7 for an example of using them.

__________Applications Information

Figures 4, 5, 6, and 7 detail how data transfer is

accomplished on the 2-wire bus. Depending upon the

state of the R/W bit, two types of data transfer are pos-

sible:

Power-Supply Decoupling

To achieve the best results when using the DS1086L,

decouple the power supply with 0.01µF and 0.1µF

high-quality, ceramic, surface-mount capacitors.

Surface-mount components minimize lead inductance,

which improves performance, and ceramic capacitors

tend to have adequate high-frequency response for

decoupling applications. These capacitors should be

placed as close to pins 3 and 4 as possible.

1) Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master

is the slave address. Next follows a number of

data bytes. The slave returns an acknowledge bit

after each received byte.

2) Data transfer from a slave transmitter to a master

receiver. The first byte (the slave address) is

transmitted by the master. The slave then returns

an acknowledge bit. Next follows a number of

data bytes transmitted by the slave to the master.

The master returns an acknowledge bit after all

received bytes other than the last byte. At the end

of the last received byte, a not acknowledge is

returned.

Stand-Alone Mode

SCL and SDA cannot be left unconnected when they

are not used. If the DS1086L never needs to be pro-

grammed in-circuit, including during production test-

ing, SDA and SCL can be tied high. The SPRD pin

must be tied either high or low.

The master device generates all the serial clock pulses

and the START and STOP conditions. A transfer is

ended with a STOP condition or with a repeated START

condition. Since a repeated START condition is also the

______________________________________________________________________________________ 15

1...12 13 141516 17

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与DS1086LU+相关器件

型号	品牌	描述	获取价格	数据表
DS1086LU+C66	MAXIM	Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, USOP-8	获取价格
DS1086LU+T	MAXIM	Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, MICRO, SOP-8	获取价格
DS1086LU-12F	ROCHESTER	SPECIALTY ANALOG CIRCUIT, PDSO8, 0.118 INCH, MICRO, SOP-8	获取价格
DS1086LU-12F+	MAXIM	Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, MICRO, SOP-8	获取价格
DS1086LU-21D+	MAXIM	Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, MICRO, SOP-8	获取价格
DS1086LU-21D+T	MAXIM	Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, MICRO, SOP-8	获取价格

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