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DS1077LU-40 PDF预览

DS1077LU-40

更新时间: 2024-02-29 16:41:37
品牌 Logo 应用领域
达拉斯 - DALLAS 外围集成电路光电二极管时钟
页数 文件大小 规格书
20页 274K
描述
3V EconOscillator/Divider

DS1077LU-40 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.25JESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
湿度敏感等级:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:40 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压:3.6 V最小供电电压:2.7 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

DS1077LU-40 数据手册

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DS1077L  
EN0 (bit)  
(Default EN0 = 1)  
If EN0 = 1 and PDN0 = 0, the CTRL0 pin functions as an output enable for OUT0, the frequency of the  
output is determined by the SEL0 bit.  
If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, output OUT0 will always be  
enabled on power-up, and its frequency is determined by the SEL0 bit.  
If EN0 = 0, the function of CTRL0 is determined by the SEL0 and PDN0 bits. (See Table 1.)  
SEL0  
(Default SEL0 = 1)  
If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX, (i.e., the output  
frequency of OUT0).  
If CTRL0 = 0, the output will be the master clock frequency.  
If CTRL0 = 1, the output will be the output frequency of the M prescaler.  
If either EN0 or PDN0 = 1, then SEL0 determines the frequency of OUT0 when it is enabled.  
If SEL0 = 0, the output will be the master clock frequency.  
If SEL0 = 1, the output will be the output frequency of the M prescaler. (See Table 1.)  
PDN0  
(Default PDN0 = 0)  
This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the  
other bits.  
If PDN0 = 0, the function of CTRL0 is determined by the values of EN0 and SEL0.  
NOTE:  
When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all  
the OUT0 circuitry is disabled even when the device is powered up. This feature can be used to save  
power when OUT0 is not used. (See Table 1.)  
PDN1  
(Default PDN1 = 0)  
If PDN1 = 1, CTRL1 will function as a power-down.  
If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only. (See Table 2.)  
NOTES (ON OUTPUT ENABLE AND POWER-DOWN):  
1. Both enables are “smart” and wait for the output to be low before going to Hi-Z.  
2. Power-down sequence first disables both outputs before powering down the device.  
3. On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles).  
4. The device cannot be programmed in power-down mode.  
5. A power-down command must persist for at least 2 cycles of the lowest output frequency plus 10µs.  
DIV WORD  
MSB  
LSB MSB  
LSB  
X
N9 N8 N7 N6 N5 N4 N3 N2 N1 N0  
first data byte  
X
X
X
X
X
second data byte  
N
These ten bits determine the value of the programmable divider (N). The range of divisor values is from 2  
to 1025, and is equal to the programmed value of N plus 2. (See Table 5.)  
6 of 20  

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