Datasheet > DS1075Z-100+

DS1075Z-100+

更新时间： 2024-01-18 10:06:43

品牌	Logo	应用领域
美信 - MAXIM		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
18页	247K
描述
Clock Generator, 100MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

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DS1075Z-100+ 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP,
针数：	8	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.73	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	端子数量：	8
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	100 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
主时钟/晶体标称频率：	50 MHz	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

DS1075Z-100+ 数据手册

DS1075

the function of the registers are described. The register settings are nonvolatile, the values being stored

automatically in EEPROM when the registers are programmed.

Note: The register bits cannot be used to make mode or frequency changes on the fly. Changes can only

be made by powering the device up in “Programming” mode. For them to be become effective the device

must then be powered down and powered up again in “Operation” mode.

For programming purposes the register bits are divided into two 9-bit words, the “MUX” word

determines mode of operation and prescaler values. The “DIV” word sets the value of the programmable

divider.

MUX WORD Figure 2

(MSB)

(LSB)

E/ I

PDN

DIV1

EN0

MSEL

* These bits must be set to zero

E/I

This bit selects either the internal oscillator or the external/ crystal reference.

1=External/Crystal

0=Internal Oscillator

however, if the PDN bit is set to zero the E/I bit will be overridden by the logic level on the

PDN /SELX pin.

Table 1

PDN /SELX

PDN

OSCILLATOR

MODE

BIT

E/I

EXTERNAL/CRYSTAL

INTERNAL

POWER-DOWN

INTERNAL

EXTERNAL/CRYSTAL

DIV1

This bit allows the master clock to be routed directly to the output (DIV1=1). The N programmable

divider is bypassed so the programmed value of N is ignored. The frequency of the output (f_OUT) will be

INTCLK or EXTCLK depending on which reference has been selected. If the Internal clock is selected

the M prescaler is also bypassed (the bit values of MSEL and M are ignored) so in this case f_OUT

=INTOSC (which also equals MCLK and INTCLK). If DIV1=0 the prescaler and programmable divider

function normally.

MSEL

This bit determines whether or not the M prescaler is bypassed. MSEL =1 will bypass the prescaler.

MSEL =0 will switch in the prescaler (unless overridden by DIV1=1), with a divide-by number

determined by the M bit.

This bit sets the divide-by number for the prescaler. M=0 results in divide-by-4, M=1 results in divide-

by-2. The setting of this bit is irrelevant if either DIV1=1 or MSEL =1.

4 of 18

1 2 345 6 7...18

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与DS1075Z-100+相关器件

型号	品牌	描述	获取价格	数据表
DS1075Z-100+T&R	MAXIM	Clock Generator, 100MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8	获取价格
DS1075Z-100IND	DALLAS	Clock Generator, 100MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8	获取价格
DS1075Z-100N	MAXIM	Analog Circuit, PDSO8, SOP-8	获取价格
DS1075Z-60	DALLAS	EconOscillator/Divider	获取价格
DS1075Z-60-IND	DALLAS	Clock Generator, 60MHz, CMOS, PDSO8,	获取价格
DS1075Z-66	DALLAS	EconOscillator/Divider	获取价格

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