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DS1005S-250 PDF预览

DS1005S-250

更新时间： 2024-11-21 04:39:07
品牌 Logo 应用领域
达拉斯 - DALLAS 延迟线
页数 文件大小 规格书
6页 65K
描述
5-Tap Silicon Delay Line

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中文翻译

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DS1005S-250 数据手册

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DS1005  
5-Tap Silicon Delay Line  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
ꢀ All-silicon time delay  
IN  
1
2
14  
13  
VCC  
NC  
IN  
1
2
16  
15  
VCC  
NC  
ꢀ 5 taps equally spaced  
ꢀ Delay tolerance ±2 ns or ±3%, whichever is  
greater  
ꢀ Stable and precise over temperature and  
voltage range  
ꢀ Leading and trailing edge accuracy  
ꢀ Economical  
ꢀ Auto-insertable, low profile  
ꢀ Standard 14-pin DIP, 8-pin DIP, or 16-pin  
SOIC  
NC  
NC  
NC  
TAP 2  
NC  
3
4
5
6
7
12  
11  
10  
9
TAP 1  
NC  
NC  
TAP 2  
NC  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
NC  
TAP 1  
NC  
TAP 3  
NC  
TAP 3  
NC  
TAP 4  
GND  
TAP 4  
NC  
8
TAP 5  
GND  
TAP 5  
DS1005 14-Pin DIP (300-mil)  
See Mech. Drawings Section  
DS1005S 16-Pin SOIC  
(300-mil)  
See Mech. Drawings Section  
ꢀ Tape and reel available for surface-mount  
ꢀ Low-power CMOS  
ꢀ TTL/CMOS compatible  
ꢀ Vapor phase, IR and wave solderability  
ꢀ Custom delays available  
ꢀ Quick turn prototypes  
1
VCC  
8
IN  
2
7
TAP 1  
TAP 3  
TAP 5  
TAP 2  
TAP 4  
GND  
3
4
6
5
ꢀ Extended temperature range available  
DS1005M 8-Pin DIP (300-mil)  
See Mech. Drawings Section  
PIN DESCRIPTION  
TAP 1-TAP 5 - TAP Output Number  
VCC  
GND  
NC  
- +5 Volts  
- Ground  
- No Connection  
- Input  
IN  
DESCRIPTION  
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns  
to 250 ns, with an accuracy of ±2 ns or ±3%, whichever is greater. This device is offered in a standard 14-  
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin  
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is  
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC  
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead  
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by  
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each  
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to  
meet special needs. For special requests and rapid delivery, call (972) 371–4348.  
1 of 6  
111799  
123456

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 		Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SO-16
DS1005S-250+ ROCHESTER

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 		SILICON DELAY LINE, TRUE OUTPUT, PDSO16, 0.300 INCH, SOIC-16
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DS1005S-60/T&R DALLAS

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DS1005S-60+T&R DALLAS

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 		Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16
DS1005S-75 DALLAS

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 		5-Tap Silicon Delay Line
DS1005S-75/T&R DALLAS

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 		Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16
DS1006 LATTICE

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 		LatticeECP2/M Family Data Sheet (Japanese Language Version)

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