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DP83924BVCE PDF预览

DP83924BVCE

更新时间: 2024-01-19 14:16:39
品牌 Logo 应用领域
美国国家半导体 - NSC 以太网
页数 文件大小 规格书
42页 420K
描述
Quad 10 Mb/s Ethernet Physical Layer - 4TPHY⑩

DP83924BVCE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QFP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm湿度敏感等级:3
功能数量:4端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):220认证状态:Not Qualified
座面最大高度:3.4 mm标称供电电压:5 V
表面贴装:YES电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子面层:TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

DP83924BVCE 数据手册

 浏览型号DP83924BVCE的Datasheet PDF文件第5页浏览型号DP83924BVCE的Datasheet PDF文件第6页浏览型号DP83924BVCE的Datasheet PDF文件第7页浏览型号DP83924BVCE的Datasheet PDF文件第9页浏览型号DP83924BVCE的Datasheet PDF文件第10页浏览型号DP83924BVCE的Datasheet PDF文件第11页 
1.0 Pin Information (Continued)  
Table 5. POWER ANDGROUND Pins (33 Pins)  
Symbol  
Pins  
Type  
Description  
NC  
NC  
NC  
NC  
NC  
48  
49  
50  
80  
81  
98  
99  
100  
NA  
No Connect;  
VDD_TPI_4 VDD_TPI_3  
VDD_TPI_2 VDD_TPI_1  
27  
21  
15  
9
P
Power for TPI Ports 1-4;  
Ground for TPI Ports 1-4;  
GND_TPI_4  
GND_TPI_3  
GND_TPI_2  
GND_TPI_1  
28  
22  
16  
10  
G
VDD_PLL_2  
VDD_PLL_1  
67  
63  
P
Power for PLL Circuitry;  
(Digital PLL)  
GND_PLL_4  
GND_PLL_3  
GND_PLL_2  
GND_PLL_1  
66  
65  
64  
62  
G
Ground for PLL Circuitry;  
(Digital PLL)  
VDD_WSPLL_1  
68  
P
Power for Wave Shaper and PLL Circuitry;  
(Analog PLL)  
GND_WSPLL_1  
VDD_WS_1  
GND_WS_1  
VDD_DIG  
69  
31  
32  
86  
85  
96  
97  
G
P
Ground for Wave Shaper and PLL Circuitry;  
Power for Wave Shaper Circuitry  
Ground for Wave Shaper Circuitry  
Power for Core Logic;  
G
P
GND_DIG  
G
G
P
Ground for Core Logic;  
GND_CLK  
Ground for Clock Circuitry;  
Power for Clock Circuitry;  
VDD_CLK  
GND_2 GND_1  
91  
53  
G
Ground for NRZ Circuitry;  
VDD_1  
70  
P
Power for NRZ Circuitry;  
Table 6. Pin Type Description  
Description  
Pin Type  
I
Input Buffer  
O
Output Buffer (driven at all times)  
I/O  
O, Z  
OD  
Bi-directional Buffer.  
Output Buffer with High Impedance Capability  
Open Drain-Like Output. Either driven Low or to a High Impedance State.  
8
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