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DP83924BVCE PDF预览

DP83924BVCE

更新时间: 2024-02-08 07:03:35
品牌 Logo 应用领域
美国国家半导体 - NSC 以太网
页数 文件大小 规格书
42页 420K
描述
Quad 10 Mb/s Ethernet Physical Layer - 4TPHY⑩

DP83924BVCE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QFP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm湿度敏感等级:3
功能数量:4端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):220认证状态:Not Qualified
座面最大高度:3.4 mm标称供电电压:5 V
表面贴装:YES电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子面层:TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

DP83924BVCE 数据手册

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1.0 Pin Information (Continued)  
1.2 Pin Description  
Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE.  
These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins)  
Symbol  
TXC  
Pin #  
Type  
Description  
77  
O
Transmit Clock: This pin outputs a 10 MHz outputclock signal synchronized to the  
transmit data (for all ports).  
TXD[4]  
TXD[3]  
TXD[2]  
TXD[1]  
40  
46  
56  
71  
I
I
Transmit Data: The serial TXD contains the transmit serial data output stream.  
TXE[4]  
TXE[3]  
TXE[2]  
TXE[1]  
41  
47  
57  
72  
Transmit Enable:This active high inputindicates the presenceof validdata on the TXD  
pins.  
CRS[4]  
CRS[3]  
CRS[2]  
CRS[1]  
43  
52  
59  
74  
O, pull-up Carrier Sense: Active high output indicates that valid data has been detected on the  
O, pull-up receive inputs.  
O, pull-up  
O, pull-up  
CRS[3:1] are dual purpose pins. When RESET is active, the value on these pins are  
sampled to determine the transceiver address for the mgmt interface. These pins have  
internal pull-ups, a 2.7 kpull down resistor is required to program a logic ‘0’.  
COL[4]  
COL[3]  
COL[2]  
COL[1]  
44  
54  
60  
75  
O, pull-up Collision: This active high output is asserted when a collision condition has been de-  
O, pull-up tected. It is also asserted for 1µs at the endof a packetto indicate the SQEtest function.  
O, pull-up  
O, pull-up  
COL[4:1] are dual purpose pins. When RESET is active, these pins are sampled and  
selects the operating mode for the device. These pins have internal pull-ups to select  
the default mode if no external pull-downs are connected. To select the non-default  
mode(s), a 2.7 kpull down resistor(s) is required. The strappable functions are:  
COL[4]; selects the number of receive clocks after carrier sense deassertion (5 RXCs  
or continuous RXCs). Default is 5 RXCs.  
COL[3]; enables or disables the receive filter. Default is to disable the receive filter.  
COL[2]; Disables Management Interface and selects the FullDuplex operating mode  
(normal or enhanced). Default is normal full duplex mode. If the enhanced Full- Duplex  
mode is selected, the functions of pins 89, 90, 92, 93, and 94 are also changed. See  
the descriptions in Sectio n3.3.13 and Se ction3.3.14.  
COL[1]; selects the LED operating mode (normal or enhanced). Default is normal LED  
mode.  
RXC[4]  
RXC[3]  
RXC[2]  
RXC[1]  
45  
55  
61  
76  
O
Receive Clock: This 10 MHz signal is generated by the transceiver, and is the recov-  
ered clock from the decoded network data stream. This signal is 10 MHz.  
The number of RXCs after the deassertion of CRS is programmable via the Global Con-  
figuration Register, GATERXC bit, D0. The options are for 5 RXCs or continuous RXCs.  
RXD[4]  
RXD[3]  
RXD[2]  
RXD[1]  
42  
51  
58  
73  
O, Pull-up Receive Data: Provides the decoded receive serial data. Data is valid on the risin  
edge of RXC.  
RXD[4:1] are dual purpose pins. When RESET is active, these pins are sampledand  
selects the operating mode for the device. These pins have internal pull-ups to select  
the default mode if no external pull-downs are connected. To select the non-default  
mode(s), a 2.7 kpull down resistor(s) is required. The strappable functions are:  
RXD[4] enables/disables Auto-Negotiation.  
RXD[3:1] selects one of five MAC interface modes. See the table in the Interface De-  
scriptions section.  
MDC  
LPBK  
93  
I
Management Data Clock: When management interface is enabled (strap option,  
COL[2]=1), this clock signal (0-2.5MHz) is the clock for transferring data across the  
management interface.  
LoopBack: When “Disable Management Interface” mode is selected (strap option,  
COL[2]=0), then this pin is an active high input to configure all ports into diagnostic loop-  
back mode.  
5
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