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DP83924BVCE PDF预览

DP83924BVCE

更新时间： 2024-02-22 12:42:14
品牌 Logo 应用领域
美国国家半导体 - NSC 以太网
页数 文件大小 规格书
42页 420K
描述
Quad 10 Mb/s Ethernet Physical Layer - 4TPHY⑩

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DP83924BVCE 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：QFP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.83
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm湿度敏感等级：3
功能数量：4端子数量：100
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：220认证状态：Not Qualified
座面最大高度：3.4 mm标称供电电压：5 V
表面贴装：YES电信集成电路类型：ETHERNET TRANSCEIVER
温度等级：COMMERCIAL端子面层：TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

DP83924BVCE 数据手册

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1.0 Pin Information (Continued)  
Table 3. LED & GENERAL CONFIGURATION Pins (8 Pins)  
Symbol  
Pins Type  
Description  
LED_DATA  
88  
O
LED serial data output: This pin outputs the serial LED data. See S ection2.3 for a de-  
scription of the LED modes. This output should be connected to the input of the 1st (ex-  
ternal) serial shift register.  
LED_CLK  
X1  
87  
95  
O
I
LED Clock: This is the clock for the serial shift registers  
External Oscillator Input: This signal is used to provide clocking signals forthe internal  
ENDEC. A 20MHz oscillator module should be used to drive this pin.  
RESET  
39  
I
I
Reset: Active low input resets the transceiver, and starts the initialization of the device.  
This pin has a noise filter on it’s input, which requires that the reset pulse must be greater  
than 30 X1 clocks.  
FDX[4:1]  
38 -35  
Full Duplex: These pins are sampled during reset. They controlthe full duplex (or half  
duplex) configuration of each port. If pulled low, Full Duplex operation is selected for the  
respective port. If pulled high, Half Duplex operation is selected. These pins have no in-  
ternal pull-up or pull-down resistors.These pins arealso used in “Enhanced full duplex”  
mode to dynamically select Full/Half duplex mode of operat i on. See Section3.3.14  
Table 4. SCAN TEST Pins (5 Pins)  
Symbol  
Pins  
Type  
Description  
TCK  
79  
I
Test Clock: This signal is used during boundary scan to clock data in and out  
of the device.  
TDI  
82  
I
Test Input:The signal contains serial data that is shifted into the device by the  
TAP controller. An internalpullup is provided if not used. It is recommended that  
during normal transceiver operation a ‘1’ should be applied to this pin.  
TDO  
TMS  
TRST  
78  
83  
84  
O,Z  
Test Output:The tristateable signalcontains serial data that is shifted out of the  
device by the TAP controller.  
I
I
Test Mode Select: This selects the operation mode of the TAP controller. An  
internal pullup is provided if not used  
Test Reset: When this signal is asserted low it forces the TAP (Test Access  
Port) controller into a logic reset state. An internal pullup is provided. This pin  
should be pulled low during normal transceiver operation.  
7
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