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DP83848YB/NOPB PDF预览

DP83848YB/NOPB

更新时间： 2024-01-23 03:39:51
品牌 Logo 应用领域
德州仪器 - TI 以太网局域网（LAN）标准以太网：16GBASE-T电信电信集成电路
页数 文件大小 规格书
89页 2852K
描述
具有 JTAG 接口、支持工作温度范围的 10/100Mbps 以太网 PHY 收发器 | PTB | 48 | -40 to 125

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DP83848YB/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：HLFQFP, QFP48,.35SQ,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.15数据速率：100000 Mbps
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
功能数量：1端子数量：48
收发器数量：1最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HLFQFP封装等效代码：QFP48,.35SQ,20
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Network Interfaces标称供电电压：3.3 V
表面贴装：YES技术：CMOS
电信集成电路类型：ETHERNET TRANSCEIVER温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

DP83848YB/NOPB 数据手册

 浏览型号DP83848YB/NOPB的Datasheet PDF文件第5页浏览型号DP83848YB/NOPB的Datasheet PDF文件第6页浏览型号DP83848YB/NOPB的Datasheet PDF文件第7页浏览型号DP83848YB/NOPB的Datasheet PDF文件第9页浏览型号DP83848YB/NOPB的Datasheet PDF文件第10页浏览型号DP83848YB/NOPB的Datasheet PDF文件第11页 
DP83848C, DP83848I  
DP83848VYB, DP83848YB  
SNLS266E –MAY 2007–REVISED MARCH 2015  
www.ti.com  
4.6 LED Interface  
See Table 6-2 for LED Mode Selection.  
SIGNAL NAME  
TYPE  
PIN #  
DESCRIPTION  
LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be  
ON when Link is good.  
LED_LINK  
S, O, PU  
28  
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive  
activity in addition to the status of the Link. The LED will be ON when Link is  
good. It will blink when the transmitter or receiver is active.  
LED_SPEED  
S, O, PU  
S, O, PU  
27  
26  
SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10  
Mb/s. Functionality of this LED is independent of mode selected.  
LED_ACT/COL  
ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity  
is  
present  
on  
either  
Transmit  
or  
Receive.  
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision  
detection. For Mode 3, this LED output may be programmed to indicate Full-  
duplex status instead of Collision.  
4.7 JTAG Interface for DP83848I/VYB/YB  
SIGNAL NAME  
TYPE  
PIN #(1)  
DESCRIPTION  
TCK  
TDI  
I, PU  
8
TEST CLOCK  
This pin has a weak internal pullup.  
TEST DATA INPUT  
I, PU  
12  
This pin has a weak internal pullup.  
TEST OUTPUT  
TDO  
TMS  
O
9
I, PU  
10  
TEST MODE SELECT  
This pin has a weak internal pullup.  
TEST RESET: Active low asynchronous test reset.  
This pin has a weak internal pullup.  
TRST#  
I, PU  
11  
(1) DP83848C does not support JTAG. Pins 8-12 should be left unconnected.  
4.8 Reset and Power Down  
SIGNAL NAME  
TYPE  
PIN #  
DESCRIPTION  
RESET_N  
I, PU  
29  
RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting  
this pin low for at least 1 µs will force a reset process to occur. All internal registers  
will re-initialize to their default states as specified for each bit in the Section 6.6  
section. All strap options are re-initialized as well.  
PWR_DOWN/INT  
I, PU  
7
See Section 7.2.1.3.1 for detailed description.  
The default function of this pin is POWER DOWN.  
POWER DOWN: The pin is an active low input in this mode and should be  
asserted low to put the device in a Power Down mode.  
INTERRUPT: The pin is an open drain output in this mode and will be asserted low  
when an interrupt condition occurs. Although the pin has a weak internal pullup,  
some applications may require an external pullup resister. Register access is  
required for the pin to be used as an interrupt mechanism. See Section 7.2.1.3.1.2  
for more details on the interrupt mechanisms.  
4.9 Strap Options  
The DP83848VYB uses many of the functional pins as strap options. The values of these pins are  
sampled during reset and used to strap the device into specific modes of operation. The strap option pin  
assignments are defined below. The functional pin name is indicated in parentheses.  
A 2.2 kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default  
option is required, then there is no need for external pullup or pulldown resistors. Since these pins may  
have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.  
8
Pin Configuration and Functions  
Copyright © 2007–2015, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB  
1...567891011...89

中文翻译

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DP83848YB/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DP83848YB TI

完全替代

 		具有 JTAG 接口、支持工作温度范围的 10/100Mbps 以太网 PHY 收发器
DP83848VYB/NOPB TI

类似代替

 		具有 JTAG 接口的高温低功耗 10/100Mbps 以太网 PHY 收发器 | PTB

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