DP83848C, DP83848I
DP83848VYB, DP83848YB
www.ti.com
SNLS266E –MAY 2007–REVISED MARCH 2015
SIGNAL
NAME
TYPE
PIN #
DESCRIPTION
TXD_0
TXD_1
TXD_2
TXD_3
I
3
4
5
6
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to
the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to
the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the
TX_CLK (10 MHz in 10 Mb/s SNI mode).
S, I, PD
O
RX_CLK
RX_DV
RX_ER
38
39
41
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5
MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for
both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.
S, O, PD
S, O, PU
MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid
indication independent of Carrier Sense.
This pin is not used in SNI mode.
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol
has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is
detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required
to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD_0
RXD_1
RXD_2
RXD_3
S, O, PD
43
44
45
46
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25
MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock,
50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0
contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
CRS/CRS_D
V
S, O, PU
S, O, PU
40
42
MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and
Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to
frame valid receive data on the RXD_0 signal.
COL
MII COLLISION DETECT: Asserted high to indicate detection of a collision condition
(simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a
duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no
heartbeat function during 10 Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will
recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine
collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition
(simultaneous transmit and receive activity) in 10 Mb/s SNI mode.
4.5 Clock Interface
SIGNAL
NAME
TYPE
PIN #
DESCRIPTION
X1
I
34
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the
DP83848C/I/VYB/YB and must be connected to a 25 MHz 0.005% (±50 ppm) clock source.
The DP83848C/I/VYB/YB supports either an external crystal resonator connected across pins
X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode
and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.
X2
O
O
33
25
CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external
25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS
oscillator clock source is used.
CLK_OUT
25 MHz CLOCK OUTPUT:
In MII mode, this pin provides a 25 MHz clock output to the system.
In RMII mode, this pin provides a 50 MHz clock output to the system.
This allows other devices to use the reference clock from the DP83848VYB without requiring
additional clock sources.
Copyright © 2007–2015, Texas Instruments Incorporated
Pin Configuration and Functions
7
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