Datasheet > DP83825IRMQR

DP83825IRMQR

更新时间： 2024-02-02 18:16:02

品牌	Logo	应用领域
德州仪器 - TI		以太网局域网（LAN）标准以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
111页	1840K
描述
具有 50MHz 速率且外形尺寸超小 (3mm x 3mm) 的低功耗 10/100Mbps 以太网 PHY 收发器 \| RMQ \| 24 \| -40 to 85

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技术参数
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DP83825IRMQR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	WQFN-24
Reach Compliance Code：	compliant	Factory Lead Time：	6 weeks
风险等级：	1.47	Samacsys Description：	DP83825I LowPower 10/100 Mbps Ethernet Physical Layer Transceiver
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e4
长度：	3 mm	湿度敏感等级：	2
功能数量：	1	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：	0.8 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	INDUSTRIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD	端子节距：	0.4 mm
端子位置：	QUAD	宽度：	3 mm
Base Number Matches：	1

DP83825IRMQR 数据手册

DP83825I

ZHCSJ67A –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

DP83825I Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

LED0 : Activity Indication LED indicates transmit and receive activity in addition to the

status of the Link. The LED is ON when Link is good. The LED blinks when the

transmitter or receiver is active. This pin can also act as GPIO through register

configuration.

Reset: I, PD, S

Active: O

LED0

This pin is at 3.3 V always and not linked to voltage supplied to VDDIO pin. This

is to avoid external components when operating PHY at VDDIO 1.8 V.

RST_N: This pin is an active low reset input. Asserting this pin low for at least 1 μs will

force a reset process to occur. Initiation of reset causes strap pins to be re-scanned

and resets all the internal registers of the PHY to default value.

Reset: I, PU

Active: I, PU

RST_N

Input Analog Supply: 3.3 V. For decoupling capacitor requirements, refer to the

Application and Implementation section.图 20

VDDA3V3

Power

RD_M

RD_P

GND

Differential Receive Input (PMD): These differential inputs are automatically configured

to accept either 10BASE-Te, 100BASE-TX specific signaling mode

GND

Ground: Connect to Ground

TD_M

TD_P

Differential Transmit Output (PMD): These differential outputs are configured to either

10BASE-Te, 100BASE-TX signaling mode based on configuration chosen for PHY.

Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin should

be left floating when a CMOS-level oscillator is connected to XI.

Crystal / Oscillator Input Clock

XI/50MHzIn

RBIAS

RMII Master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock

RMII Slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock

RBIAS value 6.49 KΩ 1% connected to ground

Reset: I, PU-

10K

Active: IO, PU-

10K

Management Data I/O: Bidirectional management data signal that may be source by

the management station or the PHY. This pin has internal pullup of 10 KΩ. External

pullup of up to 2.2 KΩ can be added if needed

MDIO

Management Data Clock: Synchronous clock to the MDIO serial management

input/output data. This clock may be asynchronous to the MAC transmit and receive

clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.

Reset: I, PD

Active: I, PD

MDC

RMII Receive Data: Symbols received on the cable are decoded and presented on

these pins synchronous to reference clock. They contain valid data when RX_DV is

asserted.

Reset: I, PD, S

Active: O

RX_D1

RMII Receive Data: Symbols received on the cable are decoded and presented on

these pins synchronous to reference clock. They contain valid data when RX_DV is

asserted.

Reset: I, PD, S

Active: O

RX_D0

VDDIO

I/O Supply : 3.3 V/1.8 V. For decoupling capacitor requirements, refer to the Application

and Implementation section.

Power

Reset: I, PD, S

Active: O

Carrier Sense / Receive Data Valid: This pin combines the RMII Carrier and Receive

Data Valid indications.

CRS_DV

GND

Ground pin

RMII Receive Error: This pin indicates an error symbol has been detected within a

received packet in RMII mode. RX_ER is asserted high synchronously to the rising

edge of the reference clock. This pin is not required to be used by the MAC in RMII

because the PHY will automatically corrupting data on a receive error.

Reset: I, PD, S

Active: O

RX_ER

Reset: I, PD

Active: I, PD

TX_D0

TX_D1

RMII Transmit Data: TX_D[1:0] received from the MAC and shall be synchronous to the

rising edge of the reference clock.

Reset: I, PD

Active: I, PD

1 2 345 6 7...111

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与DP83825IRMQR相关器件

型号	品牌	描述	获取价格	数据表
DP83825IRMQT	TI	具有 50MHz 速率且外形尺寸超小 (3mm x 3mm) 的低功耗 10/100Mbp	获取价格
DP83826E	TI	具有 MII 接口和 ENHANCED 模式的低延迟 10/100Mbps 以太网 PHY	获取价格
DP83826ERHBR	TI	具有 MII 接口和 ENHANCED 模式的低延迟 10/100Mbps 以太网 PHY	获取价格
DP83826ERHBT	TI	具有 MII 接口和 ENHANCED 模式的低延迟 10/100Mbps 以太网 PHY	获取价格
DP83826I	TI	具有工业温度范围的低延迟 10/100Mbps PHY、MII 接口和 ENHANCED	获取价格
DP83826IRHBR	TI	具有工业温度范围的低延迟 10/100Mbps PHY、MII 接口和 ENHANCED	获取价格

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