DP83822HF, DP83822IF, DP83822H, DP83822I
ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
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Table of Contents
7.19 10BASE-Te Jabber Timing......................................15
7.20 100BASE-TX Transmit Latency Timing.................. 15
7.21 100BASE-TX Receive Latency Timing................... 15
7.22 Timing Diagrams.....................................................16
7.23 Typical Characteristics............................................22
8 Detailed Description......................................................23
8.1 Overview...................................................................23
8.2 Functional Block Diagram.........................................24
8.3 Feature Description...................................................25
8.4 Device Functional Modes..........................................28
8.5 Programming............................................................ 45
8.6 Register Maps...........................................................50
9 Application and Implementation................................101
9.1 Application Information........................................... 101
9.2 Typical Applications................................................ 101
10 Power Supply Recommendations............................107
10.1 Power Supply Characteristics...............................107
11 Layout......................................................................... 112
11.1 Layout Guidelines..................................................112
11.2 Layout Example.....................................................115
12 Device and Documentation Support........................116
12.1 Related Links........................................................ 116
12.2 接收文档更新通知................................................. 116
12.3 支持资源................................................................116
12.4 Trademarks........................................................... 116
12.5 Electrostatic Discharge Caution............................116
12.6 术语表................................................................... 116
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 9
7.1 Absolute Maximum Ratings........................................ 9
7.2 ESD Ratings............................................................... 9
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information..................................................10
7.5 Electrical Characteristics...........................................10
7.6 Timing Requirements, Power-Up Timing...................11
7.7 Timing Requirements, Power-Up With Unstable
XI Clock.......................................................................12
7.8 Timing Requirements, Reset Timing.........................12
7.9 Timing Requirements, Serial Management Timing...12
7.10 Timing Requirements, 100 Mbps MII Transmit
Timing..........................................................................12
7.11 Timing Requirements, 100 Mbps MII Receive
Timing..........................................................................12
7.12 Timing Requirements, 10 Mbps MII Transmit
Timing..........................................................................13
7.13 Timing Requirements, 10 Mbps MII Receive
Timing..........................................................................13
7.14 Timing Requirements, RMII Transmit Timing..........14
7.15 Timing Requirements, RMII Receive Timing...........14
7.16 Timing Requirements, RGMII..................................14
7.17 Normal Link Pulse Timing....................................... 15
7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing......15
Information.................................................................. 117
13.1 Package Option Addendum.................................. 118
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (March 2019) to Revision F (June 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 更新了“特性”部分以突出显示关键特性。....................................................................................................... 1
• 添加了商标..........................................................................................................................................................1
• Added clarification on Tx_CLK state in reset in pin function table......................................................................4
• Added clarification on TX_CLK state in reset in IO Pins State During Reset table............................................ 4
• Added 100BASE-FX output parameters ..........................................................................................................10
• Added AVO footnote......................................................................................................................................... 11
• Added timing requirement for reset after stabilization of XI clock. ...................................................................12
• Added RMII transmit latency number .............................................................................................................. 15
• Added RGMII transmit latency number ............................................................................................................15
• Added RMII receive latency number.................................................................................................................15
• Added RGMII receive latency number..............................................................................................................15
• Updated details of earlier "reserved" bits of register 0x000B and 0x003F....................................................... 50
• Updated description for register 0x0015 and 0x001C...................................................................................... 50
• Added register description of following registers:
0x101,0x0106,0x0107,0x0126,0x04D4,0x0121,0x0122,0x0124,0x010F,0x0111,0x0129,0x0130,0x0410,0x041
6,0x0418,0x0450,0x040D ,0x041F,0x0421...................................................................................................... 50
• Added further information to registers 0x0000,0x0001,0x0469,0x0703C.........................................................50
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