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DP83630SQE/NOPB

更新时间： 2024-02-28 10:51:08
品牌 Logo 应用领域
德州仪器 - TI 以太网驱动电信接口集成电路电信电路驱动器网络接口
页数 文件大小 规格书
135页 1447K
描述
具有较小外形尺寸的 IEEE 1588 精密时间协议 (PTP) 以太网 PHY 收发器 | RHS | 48 | -40 to 85

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DP83630SQE/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
Reach Compliance Code：compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.67差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00001 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：IEEE 1588JESD-30 代码：S-PQCC-N48
JESD-609代码：e3长度：7 mm
湿度敏感等级：2功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
最大接收延迟：接收器位数：1
座面最大高度：0.8 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

DP83630SQE/NOPB 数据手册

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DP83630  
www.ti.com  
SNLS335B –OCTOBER 2010–REVISED APRIL 2013  
2.3.1 IEEE 1588 SYNCHRONIZED CLOCK  
The DP83630 provides several mechanisms for updating the IEEE 1588 clock based on the  
synchronization protocol required. These methods are listed below.  
•
•
•
•
Directly Read/Writable  
Adjustable by Add/Subtract  
Frequency Scalable  
Temporary Frequency Control  
The clock consists of the following fields: Seconds (32–bit field), Nanoseconds (30–bit field), and  
Fractional Nanoseconds (units of 2-32 ns).  
A direct set of the time value can be done by setting a new time value. A step adjustment value in  
nanoseconds may be added to the current value. Note that the adjustment value can be positive or  
negative.  
The clock can be programmed to operate at an adjusted frequency value by programming a rate  
adjustment value. The clock can also be programmed to perform a temporary adjusted frequency value by  
including a rate adjustment duration. The rate adjustment allows for correction on the order of 2-32 ns per  
reference clock cycle. The frequency adjustment will allow the clock to correct the offset over time,  
avoiding any potential side-effects caused by a step adjustment in the time value.  
The method used to update the clock value may depend on the difference in the values. For example, at  
the initial synchronization attempt, the clocks may be very far apart, and therefore require a step  
adjustment or a direct time set. Later, when clocks are very close in value, the temporary rate adjustment  
method may be the best option.  
The clock does not support negative time values. If negative time is required in the system, software will  
have to make conversions from the PHY clock time to actual time.  
The clock also does not support the upper 16-bits of the seconds field as defined by the specification  
(Version 2 specifies a 48-bit seconds field). If this value is required to be greater than 0, it will have to be  
handled by software. Since a rollover of the seconds field only occurs every 136 years, it should not be a  
significant burden to software.  
2.3.1.1 IEEE 1588 Clock Output  
The DP83630 provides for a synchronized clock signal for use by external devices. The output clock  
signal can be any frequency generated from 250 MHz divided by n, where n is an integer in the range of 2  
to 255. This provides nominal frequencies from 125 MHz down to 980.4 kHz. The clock output signal is  
controlled by the PTP_COC register. The output clock signal is generated using the rate information in the  
PTP_RATE registers and is therefore frequency accurate to the 1588 clock time of the device. In addition,  
if clock time adjustments are made using the Temporary Rate capabilities, then all time adjustments will  
be tracked by the output clock signal as well. Note that any step adjustment in the 1588 clock time will not  
be accurately represented on the 1588 clock output signal.  
2.3.1.2 IEEE 1588 Clock Input  
The IEEE 1588 PTP logic operates on a nominal 125 MHz reference clock generated by an internal Phase  
Generation Module (PGM). However, options are available to use a divided-down version of the PGM  
clock to reduce power consumption at the expense of precision, or to use an external reference clock of  
up to 125 MHz in the event the 1588 clock is tracked externally.  
Copyright © 2010–2013, Texas Instruments Incorporated  
Device Information  
7
Submit Documentation Feedback  
Product Folder Links: DP83630  
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