Datasheet > DP83561-SP

DP83561-SP

更新时间： 2022-06-24 15:42:48

品牌	Logo	应用领域
德州仪器 - TI		局域网（LAN）标准
页数	文件大小	规格书
104页	2978K
描述
DP83561-SP Radiation-Hardness-Assured (RHA), 10/100/1000 Ethernet PHY Transceiver with SEFI Handling Sub-System

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DP83561-SP 数据手册

DP83561-SP

SNLS610 – APRIL 2021

www.ti.com

Table 5-1. Pin Functions (continued)

I/O

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the

TMS pin sequences the Tap Controller (16-state FSM) to select the

desired test instruction. TI recommends that the user apply 3 clock

cycles with JTAG_TMS high to reset the JTAG.

JTAG_TMS

JTAG_TDI

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is

scanned into the device through the TDI.

COLLISION DETECT: Asserted high to indicate detection of a collision

condition (assertion of CRS due to simultaneous transmit and receive

activity) in Half-Duplex modes. This signal is not synchronous to either

MII clock (GTX_CLK, TX_CLK or RX_CLK). (Default) General Purpose

I/O: This signal provides a multi-function configurable I/O. Refer to the

GPIO_MUX_CTRL register for details.

COL/GPIO_2

CRS/GPIO_3

I/O

CARRIER SENSE: CRS is asserted high to indicate the presence of a

carrier due to receive or transmit activity in Half-Duplex mode. (Default)

General Purpose I/O: This signal provides a multi-function configurable

I/O. Please refer to the GPIO_MUX_CTRL register for details.

PD, S

0 = DP83561-SP will take no automatic action based on SEFI. SEFI

event interrupts will be generated normally. (Default)

1 = Configures the DP83561-SP to automatically apply RESET signal to

PHY logic when a SEFI is detected by one of the monitors configured

(STATE_MACHINE, temperature monitor, PLL lock, ECC registers).

Default register values will be reloaded and pin options. SEFI event

interrupts will be generated normally.

AUTO_RECOVER

PD, S

TX_D3

TX_D2

TX_D1

TX_D0

TRANSMIT DATA: Signal TX_D [3:0] carries data from the MAC to the

PHY in RGMII mode and MII mode. Data is synchronous to the transmit

clock.

RGMII TRANSMIT CLOCK: This continuous clock signal is sourced

from the MAC layer to the PHY. Nominal frequency is 125 MHz in

1000-Mbps mode. This pin will be Input in RGMII mode.

MII TRANSMIT CLOCK: In MII mode, this pin provides a 25-MHz

reference clock for 100-Mbps speed and a 2.5-MHz reference clock for

10-Mbps speed. This pin will be output in MII mode.

GTX_CLK/TX_CLK

I/O

PD/O

This pin will be GTX_CLK by default and can be changed to TX_CLK by

the GTX_CLK/TX_CLK selection without any additional register writes

needed.

I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a

1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

VDDIO_2

1.1-V Digital Supply (±5%). Each pin requires a 1-µF and 0.1-µF

capacitor to GND. Refer to Section 9 for more details.

VDD1P1_2

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与DP83561-SP相关器件

型号	品牌	描述	获取价格	数据表
DP83561-SP_V01	TI	DP83561-SP Radiation-Hardness-Assured (RHA), 10/100/1000 Ethernet PHY Transceiver with SEF	获取价格
DP83620	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQ	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQ/NOPB	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQE	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQE/NOPB	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格

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