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DP83561-SP

更新时间： 2022-06-24 15:42:48
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104页 2978K
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DP83561-SP Radiation-Hardness-Assured (RHA), 10/100/1000 Ethernet PHY Transceiver with SEFI Handling Sub-System

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DP83561-SP 数据手册

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DP83561-SP  
SNLS610 – APRIL 2021  
www.ti.com  
Table 5-1. Pin Functions (continued)  
PIN  
I/O  
TYPE(1)  
DESCRIPTION  
NO.  
NAME  
6
7
TD_M_B  
I/O  
I
A
A
Differential Transmit and Receive Signals  
Reserved. Keep it NC  
Reserved  
1.1-V Digital Supply (±5%). Each pin requires a 1-µF and 0.1-µF  
capacitor to GND. Refer to Section 9 for more details.  
8
VDD1P1_1  
I
A
9
Reserved  
TD_P_C  
TD_M_C  
I
A
A
A
Reserved. Keep it NC  
10  
11  
I/O  
I/O  
Differential Transmit and Receive Signals  
Differential Transmit and Receive Signals  
2.5-V Analog Supply (±5%). Each pin requires a 1-µF and 0.1-µF  
capacitor to GND. Refer to Section 9 for more details.  
12  
VDDA2P5_2  
I
A
13  
14  
TD_P_D  
TD_M_D  
I/O  
I/O  
A
A
Differential Transmit and Receive Signals  
Differential Transmit and Receive Signals  
Bias Resistor Connection. A 10-kΩ ±1% resistor should be connected  
from RBIAS to GND. A 90-pF ±10% capacitor should be connected in  
parallel with the bias resistor.  
15  
RBIAS  
I
A
In three-supply mode, an external 1.8-V (±5%) supply can be connected  
to these pins. When using an external supply, each pin requires a 1-µF  
and 0.1-µF capacitor to GND. Refer to Section 9 for more details.  
In two supply mode, no external supply is required for this pin.  
When unused, no connections should be made to these pins.  
16  
VDDA1P8_1  
I
A
17  
18  
19  
20  
21  
Reserved  
Reserved  
Reserved  
Reserved  
-
-
-
-
I
A
A
Reserved. Keep it NC  
Reserved. Keep it NC  
Reserved. Keep it NC  
Reserved. Keep it NC  
A
A
VDDIO_SEL_1  
A, S  
VDDIO_SEL1/ VDDIO_SEL0:  
00 (Default): VDDIO 3V3  
01: Reserve  
22  
VDDIO_SEL_0  
I
A, S  
10: VDDIO 2V5  
11: VDDIO 1V8  
0 = Dual supply mode (VDDA1P8 left floating) (Default)  
1 = Triple supply mode (VDDA1P8 supplied by system)  
23  
24  
25  
SUPPLYMODE_SEL  
VDDIO_1  
S
A
A
I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a  
1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.  
I
CRYSTAL OSCILLATOR OUTPUT: Second terminal for 25-MHz crystal.  
Must be left floating if a clock oscillator is used.  
XO  
O
26  
27  
XI  
I
A
A
CRYSTAL OSCILLATOR INPUT: 25-MHz oscillator or crystal input.  
Reserved. Keep it NC  
Reserved  
-
JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock  
source for all test logic input and output controlled by the testing entity.  
28  
JTAG_CLK  
I
PU  
JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the  
most recent test results are scanned out of the device through TDO.  
General Purpose I/O: This signal provides a multi-function configurable  
I/O. Please refer to the GPIO_MUX_CTRL register for details.  
This pin should be pulled down by a 2.49-kΩ resistor.  
29  
JTAG_TDO/GPIO_1  
O
PD  
Copyright © 2021 Texas Instruments Incorporated  
4
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Product Folder Links: DP83561-SP  
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