3.2 MULTI-CHANNEL ARCHITECTURE
2.0 Architecture Description
(Continued)
The BSI device provides three Input Channels and two Out-
put Channels, which are designed to operate independently
and concurrently. They are separately configured by the
user to manage the reception or transmission of a particular
kind of frame (for example, synchronous frames only).
The Pointer RAM Block is accessed by clearing the PTOP
(Pointer RAM Operation) bit in the Service Attention Regis-
ter, which causes the transfer of data between the Pointer
RAM Register and a mailbox location in memory.
3.3 SUPPORT FOR HEADER/INFO SPLITTING
2.3.6 Limit RAM
In order to support high performance protocol processing,
the BSI device can be programmed to split the header and
information portions of (non-MAC/SMT) frames between
two Indicate Channels. Frame bytes from the Frame Control
field (FC) up to the user-defined header length are copied
onto Indicate Channel 1, and the remaining bytes (info) are
copied onto Indicate Channel 2.
The Limit RAM Block is used by both the Indicate and Re-
quest Machines. It contains data values that define the lim-
its of the ten Queues maintained by the BSI device.
Limit RAM Registers are accessed by clearing the LMOP
(Limit RAM Operation) bit in the Service Attention Register,
which causes the transfer of data between the Limit RAM
Register and the Limit Data and Limit Address Registers.
3.4 MAC BRIDGING SUPPORT
Support for bridging and monitoring applications is provided
by the Internal/External Sorting Mode. All frames matching
the external address (frames requiring bridging) are sorted
onto Indicate Channel 2, MAC and SMT frames matching
the internal (BMAC device) address are sorted onto Indicate
Channel 0, and all other frames matching the BMAC de-
vice’s internal address (short or long) are sorted onto Indi-
cate Channel 1.
3.0 Feature Overview
The BSI device implements a system interface for the FDDI
BMAC Device. It is designed to provide a high-performance,
low-cost interface for a variety of hosts.
On the system side, the BSI device provides a simple yet
powerful bus interface and memory management scheme to
maximize system efficiency. It is capable of interfacing to a
variety of host busses/environments. The BSI device pro-
3.5 CONFIRMATION STATUS BATCHING SERVICES
vides
a 32-bit wide multiplexed address/data interface,
which can be configured to share a system bus to main
memory or communicate via external shared memory. The
system interface supports virtual addressing using fixed-size
pages.
The BSI device provides confirmation status for transmitted
and returning frames. Interrupts to the host are generated
only at status breakpoints, which are defined by the user on
a per Channel basis when the Channel is configured for
operation.
On the network side, the BSI device performs many func-
tions which greatly simplify the interface to the BMAC de-
vice, and provides many services which simplify network
management and increase system performance and reliabil-
ity. The BSI device is capable of batching confirmation and
indication status, filtering out MAC frames with the same
information field, and performing network monitoring func-
tions.
The BSI device further reduces host processing time by
separating received frame status from the received data.
This allows the CPU to quickly scan for errors when decid-
ing whether to copy the data to memory. If the status were
embedded in the data stream, all the data would need to be
read contiguously to find the Status Indicator.
3.6 RECEIVE FRAME FILTERING SERVICES
3.1 32-BIT ADDRESS/DATA PATH TO HOST MEMORY
To increase performance and reliability, the BSI device can
be programmed to filter out identical (same FC and Info
field) MAC or SMT frames received from the ring. Filtering
unnecessary frames reduces the fill rate of the Indicate
FIFO, reduces CPU frame processing time, and avoids un-
necessary memory bus transactions.
The BSI device provides a 32-bit wide synchronous multi-
plexed address/data interface, which permits interfacing to
a
standard multi-master system bus operating from
12.5 MHz to 25 MHz, or to local memory, using Big or Little
Endian byte ordering. The memory may be static or dynam-
ic. For maximum performance, the BSI device utilizes burst
mode transfers, with four or eight 32-bit words to a burst. To
assist the user with the burst transfer capability, the three
bits of the address which cycle during a burst are output
demultiplexed. Maximum burst speed is one 32-bit word per
clock, but slower speeds may be accommodated by insert-
ing wait states.
3.7 TWO TIMING DOMAINS
To provide maximum performance and system flexibility, the
BSI device utilizes two independent clocks, one for the MAC
(ring) Interface, and one for the system/memory bus. The
BSI device provides a fully synchronized interface between
these two timing domains.
The BSI device can operate within any combination of cach-
ed/non-cached, paged or non-paged memory environ-
ments. To provide this capability, all data structures are con-
tained within a page, and bus transactions never cross a
page. The BSI device performs all bus transactions within
aligned blocks to ease the interface to a cached environ-
ment.
3.8 CLUSTERED INTERRUPTS
The BSI device can be operated in a polled or interrupt-driv-
en environment. The BSI device provides the ability to gen-
erate attentions (interrupts) at group boundaries. Some
boundaries are pre-defined in hardware; others are defined
by the user when the Channel is configured. This interrupt
scheme significantly reduces the number of interrupts to the
host, thus reducing host processing overhead.
8
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