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DM74AS74SJX PDF预览

DM74AS74SJX

更新时间： 2024-11-14 22:16:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 72K
描述
Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear

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中文翻译

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DM74AS74SJX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP-14
针数：14Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.58
Is Samacsys：N系列：AS
JESD-30 代码：R-PDSO-G14JESD-609代码：e3
长度：10.2 mm逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：105000000 Hz最大I（ol）：0.02 A
湿度敏感等级：1位数：1
功能数量：2端子数量：14
最高工作温度：70 °C最低工作温度：
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：16 mA
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：2.1 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：105 MHz
Base Number Matches：1

DM74AS74SJX 数据手册

 浏览型号DM74AS74SJX的Datasheet PDF文件第2页浏览型号DM74AS74SJX的Datasheet PDF文件第3页浏览型号DM74AS74SJX的Datasheet PDF文件第4页浏览型号DM74AS74SJX的Datasheet PDF文件第5页浏览型号DM74AS74SJX的Datasheet PDF文件第6页浏览型号DM74AS74SJX的Datasheet PDF文件第7页 
April 1984  
Revised March 2000  
DM74AS74  
Dual D-Type Positive-Edge-Triggered Flip-Flop  
with Preset and Clear  
General Description  
The AS74 is a dual edge-triggered flip-flops. Each flip-flop  
has individual D, clock, clear and preset inputs, and also  
complementary Q and Q outputs.  
Features  
■ Switching specifications at 50 pF  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
Information at input D is transferred to the Q output on the  
positive going edge of the clock pulse. Clock triggering  
occurs at a voltage level of the clock pulse and is not  
directly related to the transition time of the positive going  
pulse. When the clock input is at either the HIGH or LOW  
level, the D input signal has no effect.  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
■ Functionally and pin-for-pin compatible with Schottky  
and LS TTL counterpart  
■ Improved AC performance over S74 at approximately  
half the power  
Asynchronous preset and clear inputs will set or clear Q  
output respectively upon the application of LOW level sig-  
nal.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS74M  
DM74AS74SJX  
DM74AS74N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Outputs  
PR CLR CLK  
D
X
X
X
H
L
Q
H
L
Q
L
L
H
L
H
L
X
X
X
↑
H
L
H (Note 1) H (Note 1)  
H
H
H
H
H
L
L
H
↑
H
H
L
X
Q0  
Q0  
L = LOW State  
H = HIGH State  
X = Don't Care  
↑ = Positive Edge Transition  
= Previous Condition of Q  
Q
0
Note 1: This condition is nonstable; it will not persist when preset and clear  
inputs return to their inactive (HIGH) level. The output levels in this condi-  
tion are not guaranteed to meet the V  
specification.  
OH  
© 2000 Fairchild Semiconductor Corporation  
DS006282  
www.fairchildsemi.com  
1234567

中文翻译

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