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DM74AS280 PDF预览

DM74AS280

更新时间: 2024-09-30 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 67K
描述
9-Bit Parity Generator/Checker

DM74AS280 数据手册

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October 1986  
Revised March 2000  
DM74AS280  
9-Bit Parity Generator/Checker  
General Description  
Features  
These universal, 9-bit parity generators/checkers utilize  
advanced Schottky high performance circuitry and feature  
odd/even outputs to facilitate operation of either odd or  
even parity applications. The word length capability is eas-  
ily expanded by cascading.  
Generates either odd or even parity for nine data lines  
Inputs are buffered to lower the drive requirements  
Can be used to upgrade existing systems using MSI  
parity circuits  
Cascadable for N-bits  
The DM74AS280 can be used to upgrade the performance  
of most systems utilizing the ’180 parity generator/checker.  
Although the DM74AS280 is implemented without  
expander inputs, the corresponding function is provided by  
the availability of an input at pin 4 and no internal connec-  
tion at pin 3. This permits the DM74AS280 to be substi-  
tuted for the ’180 in existing designs to produce identical  
function even if DM74AS280s are mixed with existing  
’180s.  
Advanced oxide-isolated, ion-implanted Schottky  
TTL process  
Switching specifications at 50 pF  
Switching specifications guaranteed over full  
temperature and VCC range  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS280M  
DM74AS280N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Number of Inputs (A thru I)  
that are HIGH  
Outputs  
Even  
Odd  
0, 2, 4, 6, 8  
H
L
L
1, 3, 5, 7, 9  
H
L = LOW State  
H = HIGH State  
© 2000 Fairchild Semiconductor Corporation  
DS006303  
www.fairchildsemi.com  

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