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DM74ALS163BN PDF预览

DM74ALS163BN

更新时间: 2024-11-23 22:56:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
9页 95K
描述
Synchronous Four-Bit Counter

DM74ALS163BN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.15
其他特性:TCO OUTPUT计数方向:UP
系列:ALSJESD-30 代码:R-PDIP-T16
JESD-609代码:e3长度:19.305 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:40000000 Hz最大I(ol):0.008 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:5 V最大电源电流(ICC):21 mA
传播延迟(tpd):20 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Counters
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:40 MHz
Base Number Matches:1

DM74ALS163BN 数据手册

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April 1984  
Revised February 2000  
DM74ALS161B • DM74ALS162B • DM74ALS163B  
Synchronous Four-Bit Counter  
The carry look ahead circuitry provides for cascading  
General Description  
counters for n bit synchronous application without addi-  
tional gating. Instrumental in accomplishing this function  
are two count enable inputs (P and T) and a ripple carry  
output. Both count enable inputs must be HIGH to count.  
The T input is fed forward to enable the ripple carry output.  
The ripple carry output thus enabled will produce a high  
level output pulse with a duration approximately equal to  
the high level portion of QA output. This high level overflow  
ripple carry pulse can be used to enable successive cas-  
caded stages. HIGH-to-LOW level transitions at the enable  
These synchronous presettable counters feature an inter-  
nal carry look ahead for application in high speed counting  
designs. The DM74ALS162B is a four-bit decade counter,  
while the DM74ALS161B and DM74ALS163B are four-bit  
binary counters. The DM74ALS161B clears asynchro-  
nously, while the DM74ALS162B and DM74ALS163B clear  
synchronously. The carry output is decoded to prevent  
spikes during normal counting mode of operation. Synchro-  
nous operation is provided by having all flip-flops clocked  
simultaneously so that outputs change coincident with  
each other when so instructed by count enable inputs and  
internal gating. This mode of operation eliminates the out-  
put counting spikes which are normally associated with  
asynchronous (ripple clock) counters. A buffered clock  
input triggers the four flip-flops on the rising (positive-  
going) edge of the clock input waveform.  
P
or  
T
inputs of the DM74ALS161B through  
DM74ALS163B may occur regardless of the logic level on  
the clock.  
The DM74ALS161B through DM74ALS163B feature a fully  
independent clock circuit. changes made to control inputs  
(enable P or T, or load) that will modify the operating mode  
will have no effect until clocking occurs. The function of the  
counter (whether enabled, disabled, loading or counting)  
will be dictated solely by the conditions meeting the stable  
set-up and hold times.  
These counters are fully programmable, that is, the outputs  
may be preset to either level. As presetting is synchronous,  
setting up a low level at the load input disables the counter  
and causes the outputs to agree with set up data after the  
next clock pulse regardless of the levels of enable input.  
LOW-to-HIGH transitions at the load input are perfectly  
acceptable regardless of the logic levels on the clock or  
enable inputs.  
Features  
Switching specifications at 50 pF  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
The DM74ALS161B clear function is asynchronous. A low  
level at the clear input sets all four of the flip-flop outputs  
LOW regardless of the levels of clock, load or enable  
inputs. These two counters are provided with a clear on  
power-up feature. The DM74ALS162B and DM74ALS163B  
clear function is synchronous; and a low level at the clear  
input sets all four of the flip-flop outputs LOW after the next  
clock pulse, regardless of the levels of enable inputs. This  
synchronous clear allows the count length to be modified  
easily, as decoding the maximum count desired can be  
accomplished with one external NAND gate. The gate out-  
put is connected to the clear input to synchronously clear  
the counter to all low outputs. LOW-to-HIGH transitions at  
the clear input of the DM74ALS162B and DM74ALS163B  
are also permissible regardless of the levels of logic on the  
clock, enable or load inputs.  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin-for-pin compatible with Schottky  
and low power Schottky TTL counterpart  
Improved AC performance over Schottky and low power  
Schottky counterparts  
Synchronously programmable  
Internal look ahead for fast counting  
Carry output for n-bit cascading  
Synchronous counting  
Load control line  
ESD inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS161BM  
DM74ALS161BN  
DM74ALS162BM  
DM74ALS162BN  
DM74ALS163BM  
DM74ALS163BN  
M16A  
N16E  
M16A  
N16E  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006206  
www.fairchildsemi.com  

DM74ALS163BN 替代型号

型号 品牌 替代类型 描述 数据表
DM74ALS163BMX FAIRCHILD

完全替代

Synchronous Up Counter
DM74ALS163BM FAIRCHILD

完全替代

Synchronous Four-Bit Counter
SN74ALS163BN TI

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SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

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DM74ALS1640J/A+ TI

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