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DM5495

更新时间: 2024-11-24 23:47:19
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DM5495 数据手册

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June 1989  
5495A/DM7495  
4-Bit Parallel Access Shift Registers  
General Description  
These 4-bit registers feature parallel and serial inputs, paral-  
lel outputs, mode control, and two clock inputs. The regis-  
ters have three modes of operation.  
mode control is high by connecting the output of each flip-  
flop to the parallel input of the previous flip-flop (Q to input  
D
C, etc.) and serial data is entered at input D. The clock input  
may be applied simultaneously to clock 1 and clock 2 if both  
modes can be clocked from the same source.  
Parallel (broadside) load  
Shift right (the direction Q toward Q )  
A
Shift left (the direction Q toward Q )  
D
Changes at the mode control input should normally be  
made while both clock inputs are low; however, conditions  
described in the last three lines of the truth table will also  
ensure that register contents are protected.  
D
A
Parallel loading is accomplished by applying the four bits of  
data and taking the mode control input high. The data is  
loaded into the associated flip-flops and appears at the out-  
puts after the high-to-low transition of the clock-2 input. Dur-  
ing loading, the entry of serial data is inhibited.  
Features  
Y
Typical maximum clock frequency 36 MHz  
Shift right is accomplished on the high-to-low transition of  
clock 1 when the mode control is low; shift left is accom-  
plished on the high-to-low transition of clock 2 when the  
Y
Typical power dissipation 250 mW  
Connection Diagram  
Dual-In-Line Package  
TL/F/6534–1  
Order Number 5495ADMQB, 5495AFMQB or DM7495N  
See NS Package Number J14A, N14A or W14B  
C
1995 National Semiconductor Corporation  
TL/F/6534  
RRD-B30M105/Printed in U. S. A.  

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