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DM5495

更新时间： 2024-02-24 11:41:10
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
6页 122K
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中文翻译

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DM5495 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
计数方向：BIDIRECTIONALJESD-30 代码：R-XDFP-F14
JESD-609代码：e0最大频率@ Nom-Sup：25000000 Hz
位数：4功能数量：1
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC
封装代码：DFP封装等效代码：FL14,.3
封装形状：RECTANGULAR封装形式：FLATPACK
电源：5 V认证状态：Not Qualified
筛选级别：MIL-STD-883 Class B (Modified)子类别：Shift Registers
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
Base Number Matches：1

DM5495 数据手册

 浏览型号DM5495的Datasheet PDF文件第2页浏览型号DM5495的Datasheet PDF文件第3页浏览型号DM5495的Datasheet PDF文件第4页浏览型号DM5495的Datasheet PDF文件第5页浏览型号DM5495的Datasheet PDF文件第6页 
June 1989  
5495A/DM7495  
4-Bit Parallel Access Shift Registers  
General Description  
These 4-bit registers feature parallel and serial inputs, paral-  
lel outputs, mode control, and two clock inputs. The regis-  
ters have three modes of operation.  
mode control is high by connecting the output of each flip-  
flop to the parallel input of the previous flip-flop (Q to input  
D
C, etc.) and serial data is entered at input D. The clock input  
may be applied simultaneously to clock 1 and clock 2 if both  
modes can be clocked from the same source.  
Parallel (broadside) load  
Shift right (the direction Q toward Q )  
A
Shift left (the direction Q toward Q )  
D
Changes at the mode control input should normally be  
made while both clock inputs are low; however, conditions  
described in the last three lines of the truth table will also  
ensure that register contents are protected.  
D
A
Parallel loading is accomplished by applying the four bits of  
data and taking the mode control input high. The data is  
loaded into the associated flip-flops and appears at the out-  
puts after the high-to-low transition of the clock-2 input. Dur-  
ing loading, the entry of serial data is inhibited.  
Features  
Y
Typical maximum clock frequency 36 MHz  
Shift right is accomplished on the high-to-low transition of  
clock 1 when the mode control is low; shift left is accom-  
plished on the high-to-low transition of clock 2 when the  
Y
Typical power dissipation 250 mW  
Connection Diagram  
Dual-In-Line Package  
TL/F/6534–1  
Order Number 5495ADMQB, 5495AFMQB or DM7495N  
See NS Package Number J14A, N14A or W14B  
C
1995 National Semiconductor Corporation  
TL/F/6534  
RRD-B30M105/Printed in U. S. A.  
123456

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与DM5495相关器件

型号 品牌 获取价格 描述 数据表
DM5495J TI

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 		IC 54 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14, DI
DM5495J/883 TI

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 		IC,SHIFT REGISTER,STD-TTL,DIP,14PIN,CERAMIC
DM5495J/883B ROCHESTER

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 		Parallel In Parallel Out
DM5495J/883C TI

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 		IC,SHIFT REGISTER,STD-TTL,DIP,14PIN,CERAMIC
DM5495JMIL TI

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 		54 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14, DIP-1
DM5495W NSC

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 		IC,SHIFT REGISTER,STD-TTL,FP,14PIN,CERAMIC
DM5495W TI

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 		IC,SHIFT REGISTER,STD-TTL,FP,14PIN,CERAMIC
DM5495W/883 TI

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 		IC,SHIFT REGISTER,STD-TTL,FP,14PIN,CERAMIC
DM5495W/883B ROCHESTER

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 		Parallel In Parallel Out
DM5495W/883B TI

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 		IC,SHIFT REGISTER,STD-TTL,FP,14PIN,CERAMIC

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