DM5476

更新时间： 2024-11-24 22:51:39

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
4页	111K
描述
Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

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DM5476 数据手册

June 1989

5476/DM5476/DM7476

Dual Master-Slave J-K Flip-Flops with Clear,

Preset, and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop after a complete clock

pulse. While the clock is low the slave is isolated from the

master. On the positive transition of the clock, the data from

the J and K inputs is transferred to the master. While the

clock is high the J and K inputs are disabled. On the nega-

tive transition of the clock, the data from the master is trans-

ferred to the slave. The logic state of J and K inputs must

not be allowed to change while the clock is high. The data is

transfered to the outputs on the falling edge of the clock

pulse. A low logic level on the preset or clear inputs will set

or reset the outputs regardless of the logic levels of the

other inputs.

Features

Alternate Military/Aerospace device (5476) is available.

Contact a National Semiconductor Sales Office/Distrib-

utor for specifications.

Connection Diagram

Function Table

Dual-In-Line Package

Inputs

CLK

Outputs

CLR

Toggle

High Logic Level

Low Logic Level

Either Low or High Logic Level

Positive pulse data. The J and K inputs must be held constant while

the clock is high. Data is transfered to the outputs on the falling edge of the

clock pulse.

and/or clear inputs return to their inactive (high) level.

This configuration is nonstable; that is, it will not persist when the preset

TL/F/6528–1

Order Number 5476DMQB, 5476FMQB,

DM5476J, DM5476W or DM7476N

tablished.

The output logic level before the indicated input conditions were es-

See NS Package Number J16A, N16E or W16A

each complete active high level clock pulse.

Toggle

Each output changes to the complement of its previous level on

1995 National Semiconductor Corporation

TL/F/6528

RRD-B30M105/Printed in U. S. A.

12 3 4

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与DM5476相关器件

型号	品牌	获取价格	描述	数据表
DM5476J	NSC	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM5476J/883	NSC	获取价格	TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16,
DM5476J/883B	NSC	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,STD-TTL,DIP,16PIN,CERAMIC
DM5476J-MIL	ETC	获取价格	J-K-Type Flip-Flop
DM5476W	NSC	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM5476W/883	NSC	获取价格	IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP1
DM5476W/883B	NSC	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,STD-TTL,FP,16PIN,CERAMIC
DM5476W/883C	NSC	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,STD-TTL,FP,16PIN,CERAMIC
DM5476W-MIL	ETC	获取价格	J-K-Type Flip-Flop
DM5483AJ/883	ROCHESTER	获取价格	Adder/Subtractor

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