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DM2200T1-12 PDF预览

DM2200T1-12

更新时间： 2024-02-03 03:18:21
品牌 Logo 应用领域
铁电 - RAMTRON 动态存储器静态存储器光电二极管内存集成电路
页数 文件大小 规格书
18页 150K
描述
Cache DRAM, 4MX1, 30ns, MOS, PDSO44, 0.300 INCH, PLASTIC, TSOP2-11

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DM2200T1-12 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP, TSOP44,.36,32
针数：44Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.92访问模式：FAST PAGE/STATIC COLUMN
最长访问时间：30 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH; 2K X 1 SRAM
I/O 类型：SEPARATEJESD-30 代码：R-PDSO-G44
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：CACHE DRAM内存宽度：1
功能数量：1端口数量：1
端子数量：44字数：4194304 words
字数代码：4000000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX1输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP44,.36,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：3.3 V
认证状态：Not Qualified刷新周期：1024
自我刷新：YES最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
Base Number Matches：1

DM2200T1-12 数据手册

 浏览型号DM2200T1-12的Datasheet PDF文件第2页浏览型号DM2200T1-12的Datasheet PDF文件第3页浏览型号DM2200T1-12的Datasheet PDF文件第4页浏览型号DM2200T1-12的Datasheet PDF文件第5页浏览型号DM2200T1-12的Datasheet PDF文件第6页浏览型号DM2200T1-12的Datasheet PDF文件第7页 
DM2200 EDRAM  
4Mb x 1 Enhanced Dynamic RAM  
Product Specification  
Enhanced  
Memory Systems Inc.  
Features  
■ 2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page ■ Hidden Precharge and Refresh Cycles  
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page  
■ Write Posting Register for 12ns Random Writes and Burst Writes  
Within a Page (Hit or Miss)  
■ 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache  
Fill  
■ Extended 64ms Refresh Period for Low Standby Power  
■ 300 Mil Plastic SOJ and TSOP-II Package Options  
■ +5 and +3.3 Volt Power Supply Voltage Options  
■ Low Power, Self Refresh Mode Option  
■ Industrial Temperature Range Option  
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency  
on Writes  
Description  
Architecture  
The EDRAM architecture has a simple integrated SRAM cache  
which allows it to operate much like a page mode or static column  
DRAM.  
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with  
innovative architecture to offer the optimum cost-performance solution  
for high performance local or system main memory. In most high  
speed applications, no-wait-state performance can be achieved without  
secondary SRAM cache and without interleaving main memory banks at  
system clock speeds through 50MHz. Two-way interleave will allow no-  
wait-state operation at clock speeds greater than 100MHz without the  
need of secondary SRAM cache. The EDRAM outperforms conventional  
SRAM cache plus DRAM memory systems by minimizing processor wait  
states for all possible bus events, not just cache hits. The combination  
of data and address latching, 2K of fast on-chip SRAM cache, and  
simplified on-chip cache control allows system level flexibility,  
performance, and overall memory cost reduction not available with any  
other high density memory component. Architectural similarity with  
JEDEC DRAMs allows a single memory controller design to support  
either slow JEDEC DRAMs or high speed EDRAMs. A system designed in  
this manner can provide a simple upgrade path to higher system  
performance.  
The EDRAM’s SRAM cache is integrated into the DRAM array as  
tightly coupled row registers. Memory reads always occur from the  
cache row register. When the internal comparator detects a page hit,  
only the SRAM is accessed and data is available in 12ns from column  
address. When a page read miss is detected, the new DRAM row is  
loaded into the cache and data is available at the output all within  
30ns from row enable. Subsequent reads within the page (burst reads  
or random reads) can continue at 12ns cycle time. Since reads occur  
from the SRAM cache, the DRAM precharge can occur simultaneously  
without degrading performance. The on-chip refresh counter with  
independent refresh bus allows the EDRAM to be refreshed during  
cache reads.  
Memory writes are internally posted in 12ns and directed to the  
DRAM array. During a write hit, the on-chip address comparator  
activates a parallel write path to the SRAM cache to maintain  
coherency. The EDRAM delivers 12ns cycle page mode memory  
TSOP-II Pin  
Configuration  
SOJ Pin  
Configuration  
Functional Diagram  
NC  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
V
SS *  
A
Column  
Add  
Latch  
0-10  
/CAL  
A
0
2
V
SS  
Column Decoder  
NC  
3
V
SS  
Q
D
2048 X 1 Cache (Row Register)  
A
1
4
Q
11 Bit  
Comp  
A
V
SS  
1
2
3
4
5
6
7
28  
27  
26  
25  
0
NC  
5
D
A
Q
A
3
6
NC  
NC  
NC  
/G  
V
1
Sense Amps  
& Column Write Select  
/G  
A
4
7
A
3
D
I/O  
Control  
and  
Data  
Latches  
NC  
8
A
Last  
Row  
Read  
Add  
NC  
NC  
4
A
A
5
9
0-10  
A
24  
5
/RE  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
CC  
/RE  
23 /G  
V
V
CC  
Latch  
CC  
/S  
V
V
CC  
22  
21  
20  
19  
18  
V
V
SS  
CC  
SS  
Memory  
Array  
(2048 X 2048)  
Row  
Add  
Latch  
V
V
V
V
SS  
8
SS  
SS  
SS  
/WE  
A
6
/WE  
/S  
A
6
9
/WE  
/S  
A
7
A
7
10  
11  
12  
13  
14  
A
8
/F  
A
8
/F  
NC  
NC  
W/R  
NC  
/CAL  
A
2
17 W/R  
A
2
V
CC  
A
9
A
NC  
16  
15  
/CAL  
0-9  
V
SS  
/F  
W/R  
/RE  
Row Add  
and  
Refresh  
Control  
A
9
V
A
CC  
10  
Refresh  
Counter  
V
A
CC  
10  
V
NC  
CC*  
* Reserved for future use  
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO  
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced  
80921  
38-2108-001  
The information contained herein is subject to change without notice.  
Enhanced reserves the right to change or discontinue this product without notice.  
1234567...18

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