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DLO31F-9DM1 PDF预览

DLO31F-9DM1

更新时间: 2024-11-16 09:53:27
品牌 Logo 应用领域
DATADELAY 振荡器延迟线
页数 文件大小 规格书
4页 46K
描述
TTL-INTERFACED, GATED DELAY LINE OSCILLATOR (SERIES DLO31F)

DLO31F-9DM1 数据手册

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DLO31F  
Ò
TTL-INTERFACED, GATED  
DELAY LINE OSCILLATOR  
(SERIES DLO31F)  
data  
delay  
devices,  
3
inc.  
FEATURES  
PACKAGES  
C1  
VCC  
1
7
14  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
N/C  
N/C  
N/C  
C2  
N/C  
GB  
C1  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
·
·
·
·
·
·
·
Continuous or keyable wave train  
Synchronizes with arbitrary gating signal  
Fits standard 14-pin DIP socket  
Low profile  
Auto-insertable  
Input & outputs fully TTL interfaced & buffered  
Available in frequencies from 2MHz to 40MHz  
C2  
10  
8
8
GND  
GB  
DLO31F-xx  
DIP  
Military SMD  
DLO31F-xxA2 Gull-Wing  
DLO31F-xxB2 J-Lead  
DLO31F-xxMD1  
DLO31F-xxMD4  
DLO31F-xxM Military DIP  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DLO31F-series device is a gated delay line oscillator. The device  
produces a stable square wave which is synchronized with the falling edge  
of the Gate Input (GB). The frequency of oscillation is given by the device  
dash number (See Table). The two outputs (C1,C2) are in phase during  
oscillation, but return to opposite logic levels when the device is disabled.  
GB  
C1  
C2  
Gate Input  
Clock Output 1  
Clock Output 2  
+5 Volts  
VCC  
GND Ground  
SERIES SPECIFICATIONS  
DASH NUMBER  
SPECIFICATIONS  
·
·
·
·
·
·
·
·
Frequency accuracy:  
Inherent delay (TE0):  
Output skew:  
Output rise/fall time:  
Supply voltage:  
Supply current:  
Operating temperature: 0° to 70° C  
Temperature coefficient: 100 PPM/°C (See text)  
2%  
5.5ns typical  
3.5ns typical  
2ns typical  
5VDC ± 5%  
40ma typical (7ma when disabled)  
Part  
Number  
Frequency  
(MHz)  
DLO31F-2  
DLO31F-2.5  
DLO31F-3  
DLO31F-3.5  
DLO31F-4  
DLO31F-4.5  
DLO31F-5  
DLO31F-5.5  
DLO31F-6  
DLO31F-7  
DLO31F-8  
DLO31F-9  
DLO31F-10  
DLO31F-12  
DLO31F-14  
DLO31F-15  
DLO31F-20  
DLO31F-25  
DLO31F-30  
DLO31F-35  
DLO31F-40  
2.0 ± 0.04  
2.5 ± 0.05  
3.0 ± 0.06  
3.5 ± 0.07  
4.0 ± 0.08  
4.5 ± 0.09  
5.0 ± 0.10  
5.5 ± 0.11  
6.0 ± 0.12  
7.0 ± 0.14  
8.0 ± 0.16  
9.0 ± 0.18  
10 ± 0.20  
12 ± 0.24  
14 ± 0.28  
15 ± 0.30  
20 ± 0.40  
25 ± 0.50  
30 ± 0.60  
35 ± 0.70  
40 ± 0.80  
GATE  
(GB)  
tGR  
tEO  
tDO  
CLOCK 1  
(C1)  
tCS  
1/f0  
CLOCK 2  
(C2)  
Figure 1: Timing Diagram  
NOTE: Any dash number  
between 2 and 40 not shown  
is also available.  
Ó1998 Data Delay Devices  
Doc #98001  
3/17/98  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

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