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DG508ACJZ

更新时间: 2024-11-30 03:29:31
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英特矽尔 - INTERSIL 复用器光电二极管
页数 文件大小 规格书
19页 460K
描述
CMOS Analog Multiplexers

DG508ACJZ 数据手册

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DG506A, DG507A, DG508A, DG509A  
Data Sheet  
November 1999  
File Number 3137.3  
CMOS Analog Multiplexers  
Features  
The DG506A, DG507A, DG508A and DG509A are CMOS  
Monolithic 16-Channel/Dual 8-Channel and 8-Channel/Dual  
4-Channel Analog Multiplexers, which can also be used as  
demultiplexers. An enable input is provided. When the  
enable input is high, a channel is selected by the address  
inputs, and when low, all channels are off.  
• Low Power Consumption  
• TTL and CMOS-Compatible Address and Enable Inputs  
• 44V Maximum Power Supply Rating  
• High Latch-Up Immunity  
• Break-Before-Make Switching  
• Alternate Source  
A channel in the ON state conducts current equally well in  
both directions. In the OFF state each channel blocks  
voltages up to the supply rails. The address inputs and the  
enable input are TTL and CMOS compatible over the full  
specified operating temperature range.  
Applications  
• Data Acquisition Systems  
• Communication Systems  
• Signal Multiplexing/Demultiplexing  
• Audio Signal Multiplexing  
The DG506A, DG507A, DG508A and DG509A are pinout  
compatible with the industry standard devices.  
Ordering Information  
TEMP.  
PKG.  
NO.  
TEMP.  
PKG.  
NO.  
o
o
PART NUMBER RANGE ( C)  
PACKAGE  
PART NUMBER RANGE ( C)  
PACKAGE  
DG508AAK  
DG508ABK  
DG508ACJ  
DG509ACJ  
DG509ACY  
-55 to 125 16 Ld CERDIP  
F16.3  
DG506AAK  
DG506ACJ  
DG506ACY  
DG507ABK  
DG507ACJ  
DG507ACY  
-55 to 125 28 Ld CERDIP  
F28.6  
-25 to 85  
0 to 70  
0 to 70  
0 to 70  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld PDIP  
16 Ld SOIC  
F16.3  
E16.3  
E16.3  
M16.3  
0 to 70  
0 to 70  
-25 to 85  
0 to 70  
0 to 70  
28 Ld PDIP  
28 Ld SOIC  
28 Ld CERDIP  
28 Ld PDIP  
28 Ld SOIC  
E28.6  
M28.3  
F28.6  
E28.6  
M28.3  
Pinouts  
DG506A (PDIP, CERDIP, SOIC)  
DG507A (PDIP, CERDIP, SOIC)  
DG508A (PDIP, CERDIP)  
DG509A (PDIP, SOIC)  
TOP VIEW  
TOP VIEW  
TOP VIEW  
TOP VIEW  
V+  
D
A
V+  
NC  
NC  
1
2
28 D  
1
2
28  
27  
26  
25  
A
1
2
3
4
5
6
7
8
16  
15  
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
A
A
1
1
0
0
D
B
V-  
S
27  
26  
25  
24  
23  
V-  
S
A
GND  
V+  
EN  
V-  
EN  
V-  
2
NC  
3
3
8A  
8
14 GND  
13 V+  
S
S
S
4
S
S
S
4
8B  
7B  
6B  
5B  
4B  
3B  
2B  
1B  
7A  
6A  
5A  
4A  
3A  
2A  
1A  
16  
15  
14  
13  
12  
11  
10  
7
6
5
4
3
2
1
S
1
S
1A  
S
1B  
S
S
S
S
S
S
S
24 S  
23 S  
22 S  
21 S  
5
5
S
S
S
S
S
S
S
S
2
S
S
12  
11  
10  
9
2A  
5
2B  
6
6
S
S
3
S
S
3A  
6
3B  
7
22 S  
21  
7
S
S
4
S
S
4A  
4B  
7
8
8
S
D
A
D
B
D
S
8
9
20 S  
19 S  
9
20  
19  
18  
17  
16  
15  
S
S
10  
11  
10  
11  
12  
13  
14  
18 EN  
S
EN  
9
A
0
GND 12  
17 A  
0
GND  
NC  
A
1
13  
16  
15  
A
NC  
1
2
NC  
A
2
A
A
14  
3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1

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