Datasheet > DEI1160A-SMS

DEI1160A-SMS

更新时间： 2024-02-23 13:33:05

品牌	Logo	应用领域
DEIAZ		输入元件光电二极管接口集成电路
页数	文件大小	规格书
13页	570K
描述
PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

DEI1160A-SMS 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	ESOIC-16	Reach Compliance Code：	unknown
风险等级：	5.73	其他特性：	IT ALSO OPERATE WITH 5 VOLT NOMINAL
接口集成电路类型：	INTERFACE CIRCUIT	JESD-30 代码：	R-PDSO-G16
长度：	9.9 mm	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1.75 mm	最大供电电压：	3.4 V
最小供电电压：	3.2 V	标称供电电压：	3.3 V
电源电压1-Nom：	15 V	表面贴装：	YES
温度等级：	MILITARY	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.91 mm
Base Number Matches：	1

PACKAGE DESCRIPTION - 16L Narrow Body EP SOIC

Moisture Sensitivity:

MSL 1 / 260ÛC

Ĭja:

~40ÛC/W (Mounted on 4 layer PCB with exposed pad soldered to PCB land with

thermal vias to internal GND plane)

~10ÛC/W

Ĭjc:

Lead Finish:

SnPb plated

Exposed Pad:

Electrically Isolated from IC terminals.

The PCB design and layout is a significant factor in determining thermal resistance (Ĭja) of the IC package. Use maximum

trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from

the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on the PCB.

The IC exposed pad is electrically isolated, so the PCB land may be at any potential, typically GND, for the best heat sink.

Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop down and

connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil holes on a

50mil pitch. The barrel is plated to about 1.0 ounce copper. Use as many VIAs as space allows. VIAs should be plugged to

prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary

effect. This can be avoided by tenting the VIAs with solder mask.

Figure 13 16 Lead Narrow Body EP SOIC Outline

13 of 13

DS-MW-01160-02 Rev A

03/21/2014

1...10 11 1213

下载PDF

型号	品牌	描述	获取价格	数据表
DEI1160-SES	DEIAZ	PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC	获取价格
DEI1160-SMS	DEIAZ	PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC	获取价格
DEI1166	DEIAZ	OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC	获取价格
DEI1166-TES-G	DEIAZ	OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC	获取价格
DEI1166-TMS-G	DEIAZ	OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC	获取价格
DEI1167	DEIAZ	OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC	获取价格