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DDU66C-175MD4 PDF预览

DDU66C-175MD4

更新时间： 2024-11-24 10:01:55
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DATADELAY /
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描述
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU66C)

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DDU66C-175MD4 数据手册

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DDU66C  
5-TAP, HCMOS-INTERFACED  
FIXED DELAY LINE  
(SERIES DDU66C)  
FEATURES  
PACKAGES  
IN  
VDD  
1
4
14  
12  
10  
•
•
•
•
•
Five equally spaced outputs  
Fits standard 14-pin DIP socket  
Low profile  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
T1  
IN  
N/C  
N/C  
T2  
T1  
N/C  
T3  
T2  
N/C  
T4  
T3  
Auto-insertable  
N/C  
T5  
T4  
GND  
6
7
8
GND  
Input & outputs fully CMOS interfaced & buffered  
10 T2L fan-out capability  
T5  
8
•
DDU66C-xx  
DIP  
DDU66C-xxD1  
DDU66C-xxD4  
Com. SMD  
Com. SMD  
DDU66C-xxA2 Gull-Wing  
DDU66C-xxB2 J-Lead  
DDU66C-xxMD1 Mil. SMD  
DDU66C-xxMD4 Mil. SMD  
DDU66C-xxME7Military DIP  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DDU66C-series device is a 5-tap digitally buffered delay line. The  
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an  
amount given by the device dash number. For dash numbers less than  
40, the total delay of the line is measured from T1 to T5, with the nominal  
value given by the dash number. The nominal tap-to-tap delay increment  
IN  
Signal Input  
T1-T5 Tap Outputs  
VDD +5 Volts  
GND Ground  
is given by 1/4 of this number. The inherent delay from IN to T1 is nominally 8.0ns. For dash numbers  
greater than or equal to 40, the total delay of the line is measured from IN to T5, with the nominal value  
given by the dash number. The nominal tap-to-tap delay increment is given by 1/5 of this number.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
•
•
•
•
Minimum input pulse width: 40% of total delay  
Output rise time: 8ns typical  
Part  
Total  
Delay Per  
Number  
Delay (ns)  
10 ± 2.0 *  
20 ± 2.0 *  
50 ± 3.0  
Tap (ns)  
DDU66C-10  
DDU66C-20  
DDU66C-50  
DDU66C-60  
DDU66C-75  
DDU66C-100  
DDU66C-125  
DDU66C-150  
DDU66C-175  
DDU66C-200  
DDU66C-250  
2.5 ± 1.0  
5.0 ± 2.0  
Supply voltage: 5VDC ± 5%  
Supply current:  
ICCL = 40µa typical  
10.0 ± 3.0  
12.0 ± 3.0  
15.0 ± 3.0  
20.0 ± 3.0  
25.0 ± 3.0  
30.0 ± 3.0  
35.0 ± 4.0  
40.0 ± 4.0  
50.0 ± 5.0  
ICCH = 10ma typical  
60 ± 3.0  
75 ± 4.0  
•
•
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 300 PPM/°C  
100 ± 5.0  
125 ± 6.5  
150 ± 7.5  
175 ± 8.0  
200 ± 10.0  
250 ± 12.5  
8.0ns  
25%  
25%  
25%  
25%  
* Total delay is referenced to first tap output  
Input to first tap = 8.0ns ± 2ns  
VCC IN  
T1  
T2  
T3  
T4  
T5 GND  
Functional diagram for dash numbers < 40  
NOTE: Any dash number between 10 and 250 not  
shown is also available.  
20%  
20%  
20%  
20%  
20%  
VCC IN  
T1  
T2  
T3  
T4  
T5 GND  
Functional diagram for dash numbers >= 40  
1997 Data Delay Devices  
Doc #97021  
2/5/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

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