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DAC7545KUG4 PDF预览

DAC7545KUG4

更新时间： 2024-02-03 17:43:29
品牌 Logo 应用领域
德州仪器 - TI 光电二极管转换器
页数 文件大小 规格书
9页 221K
描述
CMOS 12-Bit Multiplying D/A Converter, Microprocessor Compatible 20-SOIC -40 to 85

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中文翻译

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DAC7545KUG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP20,.4
针数：20Reach Compliance Code：compliant
风险等级：5.33转换器类型：D/A CONVERTER
输入位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输入格式：PARALLEL, WORD
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm最大线性误差 (EL)：0.0244%
湿度敏感等级：3位数：12
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V认证状态：Not Qualified
座面最大高度：2.65 mm最大稳定时间：2 µs
标称安定时间 (tstl)：2 µs子类别：Other Converters
最大压摆率：2 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

DAC7545KUG4 数据手册

 浏览型号DAC7545KUG4的Datasheet PDF文件第1页浏览型号DAC7545KUG4的Datasheet PDF文件第3页浏览型号DAC7545KUG4的Datasheet PDF文件第4页浏览型号DAC7545KUG4的Datasheet PDF文件第5页浏览型号DAC7545KUG4的Datasheet PDF文件第6页浏览型号DAC7545KUG4的Datasheet PDF文件第7页 
ABSOLUTE MAXIMUM RATINGS(1)  
TA = +25°C, unless otherwise noted.  
ELECTROSTATIC  
DISCHARGE SENSITIVITY  
VDD to DGND ........................................................................... –0.3V, +17  
Digital Input to DGND ............................................................... –0.3V, VDD  
VRFB, VREF, to DGND ........................................................................ ±25V  
This integrated circuit can be damaged by ESD. Texas Instru-  
ments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling  
and installation procedures can cause damage.  
V
PIN 1 to DGND ........................................................................ –0.3V, VDD  
AGND to DGND ........................................................................ –0.3V, VDD  
Power Dissipation: Any Package to +75°C .................................... 450mW  
Derates above +75°C by ................................ 6mW/°C  
Operating Temperature:  
ESD damage can range from subtle performance degrada-  
tion to complete device failure. Precision integrated circuits  
may be more susceptible to damage because very small  
parametric changes could cause the device not to meet its  
published specifications.  
Commercial J, K, L, and GL ........................................... –40°C to +85°C  
Storage Temperature ...................................................... –65°C to +150°C  
Lead Temperature (soldering, 10s) ............................................... +300°C  
NOTE: (1) Stresses above those listed above may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at  
these or any other condition above those indicated in the operational sections of  
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditions  
for extended periods may affect device reliability.  
PACKAGE/ORDERING INFORMATION  
SPECIFIED  
RELATIVE  
PRODUCT ACCURACY (LSB)  
GAIN ERROR (LSB)  
VDD = +5V  
PACKAGE  
PACKAGE-LEAD DESIGNATOR(1)  
TEMPERATURE PACKAGE  
RANGE MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
DAC7545  
±2  
±1  
±20  
±10  
±5  
SO-20  
DW  
"
–40°C to +85°C DAC7545JU  
DAC7545JU  
Rails, 38  
Rails, 38  
Rails, 38  
Rails, 38  
"
"
SO-20  
"
"
DAC7545KU DAC7545KU  
DAC7545  
"
±1/2  
±1/2  
DW  
"
–40°C to +85°C DAC7545LU DAC7545LU  
±2  
"
DAC7545GLU DAC7545GLU  
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.  
PIN CONNECTIONS  
Top View  
SO  
OUT 1  
AGND  
DGND  
(MSB) DB11  
DB10  
1
2
3
4
5
6
7
8
9
20 RFB  
19 VREF  
18 VDD  
17 WR  
16 CS  
DAC7545  
DB9  
15 DB0 (LSB)  
14 DB1  
13 DB2  
12 DB3  
11 DB4  
DB8  
DB7  
DB6  
DB5 10  
WRITE CYCLE TIMING DIAGRAM  
tCS  
tCH  
CS  
VDD  
0
Mode Selection  
Write Mode  
Hold Mode  
CS and WR low, DAC responds  
Data Bus (DB0-DB11) inputs.  
Either CS or WR high, data bus to  
(DB0-DB11) is locked out; DAC  
holds last data present when  
WR or CS assumed high state.  
tWR  
WR  
VDD  
0
tDH  
tDS  
NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal  
rise and fall times measured from 10% to 90% of VDD. Timing measurement  
reference level is (VIH + VIL)/2.  
VDD  
0
Data In  
(DB0-DB11  
VIH  
VIL  
Data  
Valid  
)
DAC7545  
2
SBAS150A  
www.ti.com  
1234567...9

中文翻译

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