DAC707BH/QM

更新时间： 2024-02-25 00:09:00

品牌	Logo	应用领域
BB		转换器微处理器
页数	文件大小	规格书
11页	152K
描述
D/A Converter, 1 Func, Parallel, Word Input Loading, 4us Settling Time, CDIP28,

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技术参数
数据手册

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DAC707BH/QM 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP28,.6	Reach Compliance Code：	unknown
风险等级：	5.77	最大模拟输出电压：	10 V
最小模拟输出电压：	-10 V	转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	R-CDIP-T28	JESD-609代码：	e0
最大线性误差 (EL)：	0.003%	标称负供电电压：	-15 V
位数：	16	功能数量：	1
端子数量：	28	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装等效代码：	DIP28,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5,+-15 V
认证状态：	Not Qualified	最大稳定时间：	8 µs
标称安定时间 (tstl)：	4 µs	子类别：	Other Converters
最大压摆率：	70 mA	标称供电电压：	15 V
表面贴装：	NO	技术：	BIPOLAR
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

DAC707BH/QM 数据手册

the MSB must be inverted). This code corresponds to zero

volts (DAC707 and DAC709) or zero milliamps (DAC708)

at the analog output. The maximum change in offset at t_MIN

or t_MAXis referenced to the zero error at +25°C and is divided

by the temperature change. This drift is expressed in FSR/

°C.

DISCUSSION OF

SPECIFICATIONS

DIGITAL INPUT CODES

For bipolar operation, the DAC707/708/709 accept positive-

true binary two’s complement input code. For unipolar

operation (DAC708/709 only) the input code is positive-true

straight-binary provided that the MSB input is inverted with

an external inverter. See Table I.

SETTLING TIME

Settling time of the D/A is the total time required for the

analog output to settle within an error band around its final

value after a change in digital input. Refer to Figure 1 for

typical values for this family of products.

ANALOG OUTPUT

Digital

Input

Codes

Unipolar Straight Binary⁽¹⁾

(DAC708/709 only; connected

for Unipolar operation)

Binary Two's Complement

(Bipolar operation;

all models)

7FFF_H

0000_H

FFFF_H

8000_H

+1/2 Full Scale –1LSB⁽²⁾

Zero

+Full Scale

Zero

–1LSB

+Full Scale

+1/2 Full Scale

–Full Scale

DAC707

DAC709

DAC708

NOTES: (1) MSB must be inverted externally. (2) Assumes MSB is inverted

externally.

0.1

TABLE I. Digital Input Codes.

R_L= 100Ω

ACCURACY

Linearity

R_L= 1kΩ

0.01

This specification describes one of the most important mea-

sures of performance of a D/A converter. Linearity error is

the deviation of the analog output from a straight line drawn

through the end points (–Full Scale point and +Full Scale

point).

0.001

0.01

0.1

Settling Time (µs)

FIGURE 1. Final-Value Error Band Versus Full-Scale Range

Settling Time.

Differential Linearity Error

Differential Linearity Error (DLE) of a D/A converter is the

deviation from an ideal 1LSB change in the output when the

input changes from one adjacent code to the next. A differ-

ential linearity error specification of ±1/2LSB means that the

output step size can be between 1/2LSB and 3/2LSB when

the input changes between adjacent codes. A negative DLE

specification of –1LSB maximum (–0.006% for 14-bit reso-

lution) insures monotonicity.

Voltage Output

Settling times are specified to ±0.003% of FSR (±1/2LSB

for 14 bits) for two input conditions: a full-scale range

change of 20V (±10V) or 10V (±5V or 0 to 10V) and a 1LSB

change at the “major carry”, the point at which the worst-

case settling time occurs. (This is the worst-case point since

all of the input bits change when going from one code to the

next.)

Monotonicity

Monotonicity assures that the analog output will increase or

remain the same for increasing input digital codes. The

DAC707/708/709 are specified to be monotonic to 14 bits

over the entire specification temperature range.

Current Output

Settling times are specified to ±0.003% of FSR for a full-

scale range change for two output load conditions: one for

10Ω to 100Ω and one for 1000Ω. It is specified this way

because the output RC time constant becomes the dominant

factor in determining settling time for large resistive loads.

DRIFT

Gain Drift

Gain Drift is a measure of the change in the full-scale range

output over temperature expressed in parts per million per

degree centigrade (ppm/°C). Gain drift is established by: (1)

testing the end point differences at t_MIN, +25°C and t_MAX; (2)

calculating the gain error with respect to the +25°C value;

and (3) dividing by the temperature change.

COMPLIANCE VOLTAGE

Compliance voltage applies only to current output models. It

is the maximum voltage swing allowed on the output current

pin while still being able to maintain specified accuracy.

POWER SUPPLY SENSITIVITY

Zero Drift

Power supply sensitivity is a measure of the effect of a

change in a power supply voltage on the D/A converter

Zero Drift is a measure of the change in the output with

0000_Happlied to the D/A converter inputs over the specified

temperature range. (For the DAC708/709 in unipolar mode,

DAC707/708/709

1...3 4 567 8 9...11

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与DAC707BH/QM相关器件

型号	品牌	描述	获取价格	数据表
DAC707BH-BI	BB	D/A Converter, 1 Func, Parallel, Word Input Loading, 4us Settling Time, CDIP28, HERMETIC S	获取价格
DAC707JP	BB	Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS	获取价格
DAC707JP	TI	Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS	获取价格
DAC707JP-BI	TI	Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS	获取价格
DAC707KH	TI	Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS	获取价格
DAC707KH-BI	BB	D/A Converter, 1 Func, Parallel, Word Input Loading, 4us Settling Time, CDIP28, HERMETIC S	获取价格

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