5秒后页面跳转
捷配首页

Datasheet > 转换器 > 数模转换器> DAC703KH-BI
DAC703KH-BI PDF预览

DAC703KH-BI

更新时间： 2024-01-06 17:24:57
品牌 Logo 应用领域
BB 转换器数模转换器
页数 文件大小 规格书
12页 302K
描述
Monolithic 16-Bit DIGITAL-TO-ANALOG CONVERTERS

阅读下载

获取价格

DAC703KH-BI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.62
转换器类型：D/A CONVERTER输入位码：COMPLEMENTARY OFFSET BINARY
JESD-30 代码：S-XQCC-N28JESD-609代码：e0
最大线性误差 (EL)：0.006%位数：16
功能数量：1端子数量：28
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC封装代码：QCCN
封装等效代码：LCC28,.45SQ封装形状：SQUARE
封装形式：CHIP CARRIER电源：5,+-15 V
认证状态：Not Qualified最大稳定时间：8 µs
子类别：Other Converters最大压摆率：68 mA
表面贴装：YES技术：HYBRID
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUADBase Number Matches：1

DAC703KH-BI 数据手册

 浏览型号DAC703KH-BI的Datasheet PDF文件第5页浏览型号DAC703KH-BI的Datasheet PDF文件第6页浏览型号DAC703KH-BI的Datasheet PDF文件第7页浏览型号DAC703KH-BI的Datasheet PDF文件第9页浏览型号DAC703KH-BI的Datasheet PDF文件第10页浏览型号DAC703KH-BI的Datasheet PDF文件第11页 
In many applications it is impractical to sense the output  
voltage at the output pin. Sensing the output voltage at the  
system ground point is permissible with the DAC700 family  
because the D/A converter is designed to have a constant  
return current of approximately 2mA flowing from Com-  
mon. The variation in this current is under 20µA (with  
changing input codes), therefore R4 can be as large as 3Ω  
without adversely affecting the linearity of the D/A con-  
verter. The voltage drop across R4 (R4 x 2mA) appears as a  
zero error and can be removed with the zero calibration  
adjustment. This alternate sensing point (the system ground  
point) is shown in Figures 6, 7, and 8.  
Zero Adjustment  
For unipolar (CSB) configurations, apply the digital input  
code that produces zero voltage or zero current output and  
adjust the zero potentiometer for zero output.  
For bipolar (COB, CTC) configurations, apply the digital  
input code that produces zero output voltage or current. See  
Table II for corresponding codes and the Connection Dia-  
gram for zero adjustment circuit connections. Zero calibra-  
tion should be made before gain calibration.  
Gain Adjustment  
Apply the digital input that gives the maximum positive  
output voltage. Adjust the gain potentiometer for this posi-  
tive full scale voltage. See Table II for positive full scale  
voltages and the Connection Diagram for gain adjustment  
circuit connections.  
Figures 7 and 8 show two methods of connecting the current  
output models (DAC702) with external precision output op  
amps. By sensing the output voltage at the load resistor (ie,  
by connecting RF to the output of A1 at RL), the effect of R1  
and R2 is greatly reduced. R1 will cause a gain error but is  
independent of the value of RL and can be eliminated by  
initial calibration adjustments. The effect of R2 is negligible  
because it is inside the feedback loop of the output op amp  
and is therefore greatly reduced by the loop gain.  
INSTALLATION  
CONSIDERATIONS  
This D/A converter family is laser-trimmed to 14-bit linear-  
ity. The design of the device makes the 16-bit resolution  
available. If 16-bit resolution is not required, bit 15 and bit  
16 should be connected to VDD through a single 1kΩ  
resistor.  
DAC701  
RF 5kΩ  
Due to the extremely high resolution and linearity of the  
D/A converter, system design problems such as grounding  
and contact resistance become very important. For a 16-bit  
converter with a 10V full-scale range, 1LSB is 153µV. With  
a load current of 5mA, series wiring and connector resis-  
tance of only 30mΩ will cause the output to be in error by  
1LSB. To understand what this means in terms of a system  
layout, the resistance of #23 wire is about 0.021Ω/ft. Ne-  
glecting contact resistance, less than 18 inches of wire will  
produce a 1LSB error in the analog output voltage!  
VOUT  
A1  
RDAC  
4kΩ  
R2  
R3  
RB*  
RL  
Common  
Alternate Ground  
Sense Connection  
R4  
Sense Output  
+V  
COM  
–V  
To +V  
CC  
1µF  
±15VDC  
Supply  
In Figures 6, 7, and 8, lead and contact resistances are  
represented by R1 through R5. As long as the load resistance  
RL is constant, R2 simply introduces a gain error and can be  
removed during initial calibration. R3 is part of RL, if the  
output voltage is sensed at Common, and therefore intro-  
duces no error. If RL is variable, then R2 should be less than  
1µF  
1µF  
To –V  
CC  
System Ground  
Point  
+V  
To VDD  
COM  
+5VDC  
Supply  
R
L MIN/216 to reduce voltage drops due to wiring to less than  
* RB = 2kΩ (DAC701 and DAC703)  
1LSB. For example, if RL MIN is 5kΩ, then R2 should be less  
than 0.08Ω. RL should be located as close as possible to the  
D/A converter for optimum performance. The effect of R4 is  
negligible.  
FIGURE 6. Output Circuit for Voltage Models.  
®
8
DAC701, 702, 703  
1...56789101112

下载PDF

与DAC703KH-BI相关器件

型号 品牌 描述 获取价格 数据表
DAC703KL BB D/A Converter, 16-Bit, 1 Func, Hybrid, CQCC28,

获取价格
DAC703KP BB Monolithic 16-Bit DIGITAL-TO-ANALOG CONVERTERS

获取价格
DAC703KP TI Monolithic 16-Bit DIGITAL-TO-ANALOG CONVERTERS

获取价格
DAC703KP-BI BB D/A Converter, 1 Func, Parallel, Word Input Loading, 4us Settling Time, PDIP24,

获取价格
DAC703KU TI Monolithic 16-Bit DIGITAL-TO-ANALOG CONVERTERS

获取价格
DAC703KU-BI BB D/A Converter, 1 Func, Parallel, Word Input Loading, 4us Settling Time, PDSO24,

获取价格

与DAC703KH-BI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证