DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
OUT[0:7]
NO.
5 - 8, 23 - 26
O
O
Analog DAC output voltages.
No connection.
1, 2, 3, 4, 27,
28, 29, 30
NC
VIO
9
PWR
GND
IO supply voltage. (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the device.
Ground reference point for all circuitry on the device.
GND
10, 36
Serial interface data output. The SDO pin must be enabled before operation by setting the SDO-EN bit.
Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified
by the FSDO bit (rising edge by default).
SDO
11
O
SCLK
SDI
12
13
I
I
Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK
pin.
Active low serial data enable. This input is the frame synchronization signal for the serial data. When the
signal goes low, it enables the serial interface input shift register.
CS
14
I
TOGGLE0
TOGGLE1
TOGGLE2
15
16
17
I
I
I
Toggle pins. Control signals for those DAC outputs configured for toggle operation to switch between the
two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by
Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE
pins to ground if not using the toggle operation.
Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels
configured in synchronous mode are updated simultaneously. Connect to VIO if unused.
LDAC
RESET
CLR
18
19
20
I
I
I
Active low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
Active low clear input. Logic low on this pin clears all DAC outputs to their clear code. Connect to VIO if
unused.
ALMOUT is an open drain alarm output. An external 10-kΩ pull-up resistor to a voltage no higher than VIO
is required.
ALMOUT
21
O
TEMPOUT
VCC
22
O
Analog temperature monitor output.
31, 40
32, 39
PWR
PWR
Output positive analog power supply (9 V to 41.5 V).
Output negative analog power supply (-21.5 V to 0 V).
VSS
Reference input to the device when operating with external reference. When using internal reference, this
is the reference output voltage pin. Connect a 150-nF capacitor to ground.
REF
33
34
I/O
I/O
Reference compensation capacitor connection. Connect a 330-pF capacitor between REFCMP and
REFGND.
REFCMP
REFGND
VAA
35
37
38
GND
PWR
PWR
Ground reference point for the internal reference.
Analog supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VDD pin.
Digital supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VAA pin.
VDD
THERMAL
PAD
The thermal pad is located on the package underside. The thermal pad should be connected to any
internal PCB ground plane through multiple vias for good thermal performance.
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