DAC1231LIN

更新时间： 2024-02-04 00:58:06

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器数模转换器模数转换器光电二极管
页数	文件大小	规格书
18页	362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

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技术参数
数据手册

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DAC1231LIN 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.5.B	HTS代码：	8542.39.00.01
风险等级：	5.88	Is Samacsys：	N
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	PARALLEL, 8 BITS	JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e0	长度：	26.075 mm
最大线性误差 (EL)：	0.024%	位数：	12
功能数量：	1	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	12/15 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称安定时间 (tstl)：	1 µs
子类别：	Other Converters	最大压摆率：	2.5 mA
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

DAC1231LIN 数据手册

All of the digital inputs to these DACs contain a unique

threshold regulator circuit to maintain TTL voltage level

Application Hints

1.0 DIGITAL INTERFACE

compatibility independent of the applied V

to the DAC.

Any input can also be driven from higher voltage CMOS

logic levels in non-microprocessor based systems. To pre-

vent damage to the chip from static discharge, all unused

These DACs are designed to provide all of the necessary

digital input circuitry to permit a direct interface to a wide

variety of microprocessor systems. The timing and logic lev-

el convention of the input control signals allow the DACs to

be treated as a typical memory device or I/O peripheral with

no external logic required in most systems. Essentially

these DACs can be mapped as a two-byte stack in memory

(or I/O space) to receive their 12 bits of input data in two

successive 8-bit data writing sequences. The DAC1230 se-

ries is intended for use in systems with an 8-bit data bus.

The DAC1208 series provides all 12 digital input lines which

can be externally configured to be controlled from an 8-bit

bus or can be driven directly from a 16-bit data bus.

digital inputs should be tied to V or ground. As a trouble-

shooting aid, if any digital input is inadvertently left floating,

the DAC will interpret the pin as a logic ‘‘1’’.

Double buffered digital inputs allow the DAC to internally

format the 12-bit word used to set the current switching R-

2R ladder network (see section 2.0) from two 8-bit data

write cycles. Figures 1 and 2 show the internal data regis-

ters and their controlling logic circuitry. The timing diagrams

for updating the DAC output are shown in sections 1.1, 1.2

and 1.3 for three possible control modes. The method used

depends strictly upon the particular application.

FIGURE 1. DAC1208, DAC1209, DAC1210 Functional Diagram

TL/H/5690–6

FIGURE 2. DAC1230, DAC1231, DAC1232 Functional Diagram

1...3 4 567 8 9...18

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与DAC1231LIN相关器件

型号	品牌	描述	获取价格	数据表
DAC1232	ETC		获取价格
DAC1232LCD	TI	IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,DIP,20PIN	获取价格
DAC1232LCD/A+	TI	IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,DIP,20PIN	获取价格
DAC1232LCJ	NSC	12-Bit, uP Compatible, Double-Buffered D to A Converters	获取价格
DAC1232LCJ/A+	TI	IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,DIP,20PIN	获取价格
DAC1232LCJ-1	NSC	12-Bit, uP Compatible, Double-Buffered D to A Converters	获取价格

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