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DAC1231LIN

更新时间： 2024-01-12 13:23:52
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器数模转换器模数转换器光电二极管
页数 文件大小 规格书
18页 362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

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中文翻译

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DAC1231LIN 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP20,.3Reach Compliance Code：unknown
ECCN代码：3A001.A.5.BHTS代码：8542.39.00.01
风险等级：5.88Is Samacsys：N
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：PARALLEL, 8 BITSJESD-30 代码：R-PDIP-T20
JESD-609代码：e0长度：26.075 mm
最大线性误差 (EL)：0.024%位数：12
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：12/15 V认证状态：Not Qualified
座面最大高度：5.08 mm标称安定时间 (tstl)：1 µs
子类别：Other Converters最大压摆率：2.5 mA
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

DAC1231LIN 数据手册

 浏览型号DAC1231LIN的Datasheet PDF文件第10页浏览型号DAC1231LIN的Datasheet PDF文件第11页浏览型号DAC1231LIN的Datasheet PDF文件第12页浏览型号DAC1231LIN的Datasheet PDF文件第14页浏览型号DAC1231LIN的Datasheet PDF文件第15页浏览型号DAC1231LIN的Datasheet PDF文件第16页 
Application Hints (Continued)  
Transient response and settling time of the op amp are im-  
portant in fast data throughput applications. The largest sta-  
bility problem is the feedback pole created by the feedback  
internal feedback resistor, R , matches the R-2R ladder  
Fb  
resistors. A negative gain error indicates that R is a small-  
Fb  
er resistance value than it should be. To adjust this gain  
error, some resistance must always be added in series with  
resistance, R , and the output capacitance of the DAC.  
Fb  
b
This appears from the op amp output to the ( ) input and  
includes the stray capacitance at this node. Addition of a  
R . The 50X potentiometer shown is sufficient to adjust  
Fb  
the worst-case gain error for these devices.  
lead capacitance, C in Figure 9, greatly reduces overshoot  
C
and ringing at the output for a step change in DAC output  
current.  
2.2 Bipolar Output Voltage from a Fixed Reference  
The addition of a second op amp to the unipolar circuit can  
generate a bipolar output voltage from a fixed reference  
voltage. This, in effect, gives sign significance to the MSB of  
the digital input word to allow two quadrant multiplication of  
the reference voltage. The polarity of the reference can also  
be reversed to realize full 4-quadrant multiplication. This cir-  
cuit is shown in Figure 10.  
2.1.1 Zero and Full-Scale Adjustments  
For accurate conversions, the input offset voltage of the  
output amplifier must always be nulled. Amplifier offset er-  
rors create an overall degradation of DAC linearity.  
The fundamental purpose of zeroing is to make the voltage  
as possible.  
appearing at the DAC outputs as near 0 V  
DC  
This configuration features several improvements over ex-  
isting circuits for a bipolar output shown with other multiply-  
ing DACs. Only the offset voltage of amplifier 1 affects the  
linearity of the DAC. The offset voltage error of the second  
op amp (although a constant output error) has no effect on  
linearity. In addition, this configuration offers a non-interac-  
tive positive and negative full-scale calibration procedure.  
This is accomplished by shorting out R , the amplifier feed-  
Fb  
back resistor, and adjusting the v nulling potentiometer of  
OS  
the op amp until the output reads zero volts. This is done, of  
course, with an applied digital code of all zeros if I  
OUT1  
is  
driving the op amp (all ones for I  
R
). The short around  
OUT2  
is then removed and the converter is zero adjusted.  
Fb  
A unique feature of this series of DACs is that the full-scale  
or gain error is guaranteed to be negative. The gain error  
specification is a measure of how close the value of the  
b
D
2048 TL/H/5690-16  
e
V
V
REF  
OUT  
2048  
#
J
s
s
for 0  
D
4095  
V
l
REF  
l
e
1 LSB  
2048  
Input Code  
MSB......LSB  
Ideal V  
OUT  
a
b
V
REF  
V
REF  
b
b
a
REF  
1 1 1 1 1 1 1 1 1 1 1 1  
1 1 0 0 0 0 0 0 0 0 0 0  
1 0 0 0 0 0 0 0 0 0 0 0  
0 1 1 1 1 1 1 1 1 1 1 1  
0 0 1 1 1 1 1 1 1 1 1 1  
0 0 0 0 0 0 0 0 0 0 0 0  
V
1 LSB  
/2  
V
1 LSB  
/2  
REF  
l
l
b
V
V
REF  
REF  
0
l
l
0
b
REF  
a
1 LSB  
1 LSB  
V
V
l
REF  
l
b
b
a
1 LSB  
1 LSB  
2
b
2
a
V
REF  
V
REF  
l
l
FIGURE 10. Bipolar Output Voltage Configuration  
13  
1...10111213141516...18

中文翻译

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