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DAC102S085CIMMX PDF预览

DAC102S085CIMMX

更新时间: 2024-01-28 03:51:03
品牌 Logo 应用领域
德州仪器 - TI 转换器数模转换器光电二极管
页数 文件大小 规格书
28页 1135K
描述
DAC102S085 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail

DAC102S085CIMMX 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SON
包装说明:LLP-10针数:10
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.14
Is Samacsys:N最大模拟输出电压:5.5 V
最小模拟输出电压:转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:S-PDSO-N10JESD-609代码:e0
长度:3 mm最大线性误差 (EL):0.1953%
湿度敏感等级:1位数:10
功能数量:1端子数量:10
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVSON
封装等效代码:SOLCC10,.11,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:0.8 mm最大稳定时间:6 µs
标称安定时间 (tstl):4.5 µs子类别:Other Converters
最大压摆率:0.41 mA标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmBase Number Matches:1

DAC102S085CIMMX 数据手册

 浏览型号DAC102S085CIMMX的Datasheet PDF文件第1页浏览型号DAC102S085CIMMX的Datasheet PDF文件第3页浏览型号DAC102S085CIMMX的Datasheet PDF文件第4页浏览型号DAC102S085CIMMX的Datasheet PDF文件第5页浏览型号DAC102S085CIMMX的Datasheet PDF文件第6页浏览型号DAC102S085CIMMX的Datasheet PDF文件第7页 
DAC102S085  
SNAS364E MAY 2006REVISED MARCH 2013  
www.ti.com  
Block Diagram  
V
REFIN  
DAC102S085  
REF  
10 BIT DAC  
POWER-ON  
RESET  
BUFFER  
V
OUTA  
10  
2.5k  
2.5k  
100k  
100k  
REF  
10 BIT DAC  
DAC  
REGISTER  
BUFFER  
V
OUTB  
10  
10  
POWER-DOWN  
CONTROL  
LOGIC  
INPUT  
CONTROL  
LOGIC  
SCLK  
SYNC  
D
IN  
PIN DESCRIPTIONS  
SON  
VSSOP  
Pin No.  
Symbol  
Type  
Description  
1
2
3
4
5
6
VA  
VOUTA  
VOUTB  
NC  
Supply  
Power supply input. Must be decoupled to GND.  
Channel A Analog Output Voltage.  
Channel B Analog Output Voltage.  
Not Connected  
Analog Output  
Analog Output  
NC  
Not Connected  
GND  
Ground  
Ground reference for all on-chip circuitry.  
Unbuffered reference voltage shared by all channels. Must be decoupled  
to GND.  
7
8
VREFIN  
DIN  
Analog Input  
Serial Data Input. Data is clocked into the 16-bit shift register on the  
falling edges of SCLK after the fall of SYNC.  
Digital Input  
Frame synchronization input for the data input. When this pin goes low, it  
enables the input shift register and data is transferred on the falling edges  
of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is  
brought high before the 16th clock, in which case the rising edge of  
SYNC acts as an interrupt and the write sequence is ignored by the DAC.  
9
SYNC  
SCLK  
Digital Input  
Serial Clock Input. Data is clocked into the input shift register on the  
falling edges of this pin.  
10  
11  
Digital Input  
Ground  
Exposed die attach pad can be connected to ground or left floating.  
Soldering the pad to the PCB offers optimal thermal performance and  
enhances package self-alignment during reflow.  
PAD  
(SON only)  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
2
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Copyright © 2006–2013, Texas Instruments Incorporated  
Product Folder Links: DAC102S085  

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