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D824L8L-4 PDF预览

D824L8L-4

更新时间: 2024-02-11 21:24:38
品牌 Logo 应用领域
FREQUENCYDEVICES /
页数 文件大小 规格书
13页 535K
描述
2" x 2" Differential Input 4-Pole Filters

D824L8L-4 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:XMA, MODULE,9LEAD,2SQReach Compliance Code:unknown
风险等级:5.78Is Samacsys:N
JESD-30 代码:S-PXMA-P15长度:50.8 mm
负电源电压最大值(Vsup):-18 V负电源电压最小值(Vsup):-12 V
标称负供电电压 (Vsup):-15 V功能数量:1
端子数量:15最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC
封装代码:XMA封装等效代码:MODULE,9LEAD,2SQ
封装形状:SQUARE封装形式:MICROELECTRONIC ASSEMBLY
电源:+-15 V认证状态:Not Qualified
座面最大高度:1.27 mm子类别:Active Filters
最大供电电流 (Isup):20 mA最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):12 V标称供电电压 (Vsup):15 V
表面贴装:NO技术:HYBRID
温度等级:COMMERCIAL端子形式:PIN/PEG
宽度:50.8 mmBase Number Matches:1

D824L8L-4 数据手册

 浏览型号D824L8L-4的Datasheet PDF文件第1页浏览型号D824L8L-4的Datasheet PDF文件第3页浏览型号D824L8L-4的Datasheet PDF文件第4页浏览型号D824L8L-4的Datasheet PDF文件第5页浏览型号D824L8L-4的Datasheet PDF文件第6页浏览型号D824L8L-4的Datasheet PDF文件第7页 
D824 Series  
Digital Tuning &  
8-Bit Programmable Filters  
Control Characteristics  
Pin-Out Key  
Digital Tuning Characteristics  
IN  
Analog Input Signal  
D7 Tuning Bit 7 (MSB)  
D6 Tuning Bit 6  
D5 Tuning Bit 5  
D4 Tuning Bit 4  
D3 Tuning Bit 3  
The digital tuning interface circuits are a parallel set of eight (8)  
4053 CMOS switches which accept CMOS compatible inputs  
for the eight tuning bits (D0 - D7).  
OUT Analog Output Signal  
GND Power and Signal Return  
+Vs Supply Voltage, Positive  
-Vs Supply Voltage, Negative  
Filter tuning follows the tuning equation given below:  
Os  
Offset Adjustment  
D2 Tuning Bit 2  
D1 Tuning Bit 1  
D0 Tuning Bit 0 (LSB)  
fc = ( fmax/256 ) [ 1 + D7 x 27 + D6 x 26 + D5 x 25 + D4 x 24 + D3  
x 23 + D2 x 22 + D1 x 21 + D0 x 20 ]  
where D1 - D7 = "0" or "1", and  
OUT +Vs  
-Vs  
fmax = Maximum tuning frequency;  
fc = corner frequency;  
D7  
D6  
D5  
Minimum tunable frequency = fmax/256 (D0 thru D7 = 0);  
Minimum frequency step (Resolution) = fmax/256  
D4  
GND  
D3  
D2  
D1  
D0  
Data Input Specifications  
2.00  
Input Data Levels  
(CMOS Logic)  
Input Voltage (Vs = 15 Vdc)  
Low Level In  
High Level In  
0 Vdc min.  
11 Vdc min.  
4 Vdc max.  
15 Vdc max.  
Input Current  
High Level In  
Low Level In  
+IN-IN Os4  
- 10 -5 mA typ. -1 mA max..  
+10 -5 mA typ. +1 mA max.  
Bottom View  
Input Capacitance  
Input Data Format  
Positive Logic  
5 pF typ  
7.5 pF max.  
Bit  
MSB ---  
---  
---  
---  
---  
---  
LSB  
Frequency Select Bits  
Weight  
Logic "1" = +Vs  
Logic "0" = Gnd  
27  
26  
25  
24  
23  
22  
21  
20  
fc  
Corner  
Frequency  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Bit Weighting  
D0  
(Binary-Coded)  
LSB (least significant bit)  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
fmax/256  
fmax/128  
fmax/64  
fmax/32  
fmax/16  
fmax/8  
D7  
MSB (most significant bit)  
Frequency Range  
256 : 1, Binary Weighted  
fmax/4  
fmax/2  
fmax  
2
1784 Chessie Lane, Ottawa, IL 61350 • Tel: 800/252-7074, 815/434-7800 • FAX: 815/434-8176  
e-mail: sales@freqdev.com • Web Address: http://www.freqdev.com  

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