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D8254 PDF预览

D8254

更新时间: 2024-02-15 08:53:45
品牌 Logo 应用领域
DCD /
页数 文件大小 规格书
4页 137K
描述
Programmable Interval Timer

D8254 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERDIP-24
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:8.16其他特性:6 PROGRAMMABLE MODES
外部数据总线宽度:8信息访问方法:PARALLEL, DIRECT ADDRESS
JESD-30 代码:R-GDIP-T24JESD-609代码:e0
位数:16端子数量:24
计时器数量:3最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified最大压摆率:170 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:NMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
uPs/uCs/外围集成电路类型:TIMER, PROGRAMMABLEBase Number Matches:1

D8254 数据手册

 浏览型号D8254的Datasheet PDF文件第2页浏览型号D8254的Datasheet PDF文件第3页浏览型号D8254的Datasheet PDF文件第4页 
D8254  
Programmable Interval Timer  
ver 1.08  
Simple interface allows easy connection  
O V E R V I E W  
to microcontrollers  
The D8254 is a programmable interval  
timer/counter, binary compatible with industry  
standard 82C54. The D8254 solves one of  
the most common problems in any micro-  
computer system, the generation of accurate  
time delays under software control. The  
D8254 can be used as a:  
Fully synthesizable, static design with no  
internal tri-states  
D E L I V E R A B L E S  
Source code:  
VHDL Source Code or/and  
VERILOG Source Code or/and  
Encrypted, or plain text EDIF netlist  
VHDL & VERILOG test bench environ-  
ment  
Real time clock  
Even counter  
Digital one-shot  
Programmable rate generator  
Square wave generator  
Binary rate multiplier  
Complex waveform generator  
Complex motor controller  
Active-HDL automatic simulation mac-  
ros  
ModelSim automatic simulation macros  
Tests with reference responses  
Technical documentation  
Installation notes  
HDL core specification  
Datasheet  
Synthesis scripts  
Example application  
Technical support  
K E Y F E A T U R E S  
Three independent 16-bit counters  
IP Core implementation support  
3 months maintenance  
Delivery the IP Core updates, mi-  
nor and major versions changes  
Delivery the documentation up-  
dates  
Six programmable Counter modes  
Interrupt on terminal count  
Hardware retriggerable One-Shot  
Rate Generator  
Phone & email support  
Square wave mode  
Software triggered strobe  
Hardware triggered strobe  
Binary or BCD counting  
Status Read Back Command  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.  

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