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CYWB0224ABS-BVXI

更新时间： 2024-02-18 11:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
6页	229K
描述
West BridgeTM AstoriaTM

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技术参数
数据手册

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CYWB0224ABS-BVXI 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.62
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

CYWB0224ABS-BVXI 数据手册

ADVANCE INFORMATION

CYWB0224ABS/CYWB0224ABM

SD/SDIO/MMC+/CE-ATA Port (S-Port)

West Bridge Astoria provides support for 1-bit and 4-bit SD and

SDIO cards; 1-bit, 4-bit and 8-bit MMC; MMC+ cards, and

CE-ATA drive. For the SD, SDIO, MMC/MMC Plus, and CE-ATA,

this block supports one card for one physical bus interface.

When Astoria is configured through firmware to support

SD/SDIO/MMC+/CE-ATA, this interface supports the following:

■ The Multimedia Card System Specification, MMCA Technical

Committee, Version 4.1.

Astoria supports SD commands including the multisector

program command, which is handled by API.

■ SD Memory Card Specification - Part 1, Physical Layer

Specification, SD Group, Version 1.10, October 15, 2004.

■ SD Memory Card Specification - Part 1, Physical Layer

Specification, SD Group, Version 2.0, May 9, 2006.

■ SD Specifications - Part E1 SDIO specification, Version 1.10,

August 18, 2004.

■ CE-ATA Specification - CE-ATA Digital Protocol, CE-ATA

Committee, Version 1.1, September, 2005

Table 1. Astoria Pin Assignments

Pin Name

Pin Description

Clock/SPI clock

Power Domain

Non-multiplexing Multiplexing

SRAM

PNAND

Ext pull up

SPI

CLK

CE#

CLK

CE#

SCK

SS#

CE#

CS#

Chip Enable/NAND Chip Select/SPI Slave

Select

Ext pull up

CLE#

Ext pull up

set A[3:2] = 10

Ext pull up

SCL

Address Bus 0/PNAND Command Latch

Address Bus 1/PNAND Ready_Buy

Addr. Bus [3:2]

RB#

A[3:2]

set A[3:2] = 01 A[3:2]

set A[3:2] = 00

WP#

Ext pull up

SCL

Addr. Bus 4/NAND Write Protect

Address Bus 5/I2C clock

Address Bus 6/I2C data

Addr. Bus 7

SCL

SDA

A7]

Ext pull up

set A7 to 0 - LBD Ext pull up

set A7 to 1 - SBD

PVDDQ

VGND

DQ[0]

DQ[1]

DQ[15:2]

ADV#

OE#

AD[0]

AD[1]

AD[15:2]

ADV#

OE#

DQ[0]

DQ[1]

IO[0]

SDI

SPI Input/Data Bus 0

SPI Output/Data Bus 1

Data Bus

IO[1]

SDO

DQ[15:2]

IO[15:2]

ALE#

RE#

Ext pull up

SINT

Address Valid

OE#

Output Enable

WE#

Write Enable

INT#

Interrupt Request

DMA Request

DRQ#

DACK#

D+

DRQ#

DACK#

DRQ#

DACK#

DRQ#

DACK#

N/C

Ext pull up

DMA Acknowledgement

IO/Z USB D+

IO/Z USB D-

UVDDQ

UVSSQ

D-

UVALID

External USB Switch Control

Document #: 001-11710 Rev. *A

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