Datasheet > CYRS16B512-133FZMB

CYRS16B512-133FZMB

更新时间： 2023-12-06 20:12:30

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
140页	1189K
描述
Quad SPI Flash

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CYRS16B512-133FZMB 数据手册

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CYRS16B512

4. Block Diagrams

4.1

Logic Block Diagram

Figure 2. Logic Block Diagram Quad-SPI

CS#

SCK

Memory Array

SI/IO0

SO/IO1

WP#/IO2

Y Decoders

Data Latch

I/O

Control

Logic

RESET#/IO3

Data Path

RESET#

4.2

System Block Diagram

Figure 3. SPI Host and SPI Device with Dual CS#, SCK and RESET#^{[4, 5]}

IO0 – IO3

Quad SPI-1

SCK1

SCK

CS#

CS1#

RESET1#

RESET#

RESET2#

CS2#

SCK2

Quad SPI-2

IO4 – IO7

SPI HOST

Dual-Quad SPI Device

Notes

4. For the 36L Flatpack Package

5. The SPI Host outputs one Chip Select (CS#) signal, that is routed to CS1# and CS2# balls on the Dual-Quad SPI device. The SPI Host outputs one Clock (SCK)

signal, that is routed to SCK1 and SCK2 balls on the Dual-Quad SPI device. The SPI Host outputs one reset (RESET#) signal, that is routed to RESET1# and

RESET2# on the Dual-Quad SPI device.

Document Number: 002-18540 Rev. *B

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