CYRS16B512
3. Signal Descriptions
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large
number of signal connections and larger package size. The large number of connections increase power consumption due to so many
signals switching and the larger package increases cost.
The CY16B family reduces the number of signals for connection to the host system by serially transferring all control, address, and
data information over 10 (single CS# & SCK) signals. The CYRS16B512 SPI device uses the industry standard single bit Serial
Peripheral Interface (SPI) using two Quad SPI devices in each package (Quad SPI-1 & Quad SPI-2). This interface is called Dual-
Quad SPI and enables support of Byte wide (8 bit) serial transfers. There ceramic package option available is:
■ 36 Lead Flatpack package with separate leads for CS1#, SCK1, RESET1# (Quad SPI-1) and CS2#, SCK1, RESET2# (Quad SPI-2).
For documentation simplicity, all AC timings and waveforms and DC specification are defined using single CS# (Chip Select) and SCK
(Serial Clock) signals. The CS#, SCK, and RESET# signals for Quad SPI-1 and Quad SPI-2 need to be externally tied together to
operate in Dual-Quad mode utilizing eight I/Os.
3.1
Input/Output Summary
Table 2. SPI Input/Output Descriptions
Signal Name
Type
Description
Hardware Reset: Low = device resets and returns to standby state, ready to receive a command. The signal
has an internal pull-up resistor and may be left unconnected in the host system if not used.
RESET#
Input
SCK1
SCK2
CS1#
CS2#
IO0
Input
Input
Input
Input
I/O
Serial Clock for Quad SPI-1[3]
Serial Clock for Quad SPI-2[3]
Chip Select for Quad SPI-1[3]
Chip Select for Quad SPI-2[3]
I/O 0 for Quad SPI-1
I/O 1 for Quad SPI-1
I/O 2 for Quad SPI-1
I/O 3 for Quad SPI-1
I/O 0 for Quad SPI-2
I/O 1 for Quad SPI-2
I/O 2 for Quad SPI-2
I/O 3 for Quad SPI-2
Core Power Supply.
Ground.
IO1
I/O
IO2
I/O
IO3
I/O
IO4
I/O
IO5
I/O
IO6
I/O
IO7
I/O
VDD
VSS
Supply
Supply
Not Connected.
No device internal signal is connected to the package connector nor is there any future plan to use the
connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit
Board (PCB). However, any signal connected to a NC pin must not have voltage levels higher than the VCC
absolute maximum on page 1 (Supply Voltage).
NC
Unused
Reserved for Future Use.
No device internal signal is currently connected to the package connector but there is potential future use for
the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that
the PCB may take advantage of future enhanced features in compatible footprint devices.
RFU
Reserved
Do Not Use.
A device internal signal may be connected to the package connector. The connection may be used by
Cypress for test or other purposes and is not intended for connection to any host system signal. Any DNU
signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor
and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB
signal routing channels. Do not connect any host system signal to this connection.
DNU
Reserved
Notes
2. Inputs with internal pull-ups or pull-downs drive less than 2uA. Only during power-up is the current larger at 150uAfor 4uS. Resistance of pull-ups or pull-down resistors
with the typical process at Vcc= 3.3V at -40°C is ~4.5 Mohms and at 90°C is ~6.6Mohms.
3. For the 36L Flatpack Package there are two CS# and two SCK leads.
Document Number: 002-18540 Rev. *B
Page 6 of 139
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